Avoid potential slient wrong-code with reg+reg addr. modes on SH.

gcc/
	* config/sh/sh.c (sh_print_operand_address): Don't use hardcoded 'r0'
	for reg+reg addressing mode.

From-SVN: r237088

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6d3974b875ec87bd96d79b03a25c1db3e1ef5777..bce140bef53a65fe0967da256c105ddcca845d8f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2016-06-04  Oleg Endo  <olegendo@gcc.gnu.org>
+
+       * config/sh/sh.c (sh_print_operand_address): Don't use hardcoded 'r0'
+       for reg+reg addressing mode.
+
 2016-06-03  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
 
        * rs6000-c.c (c/c-tree.h): Add #include.

diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 2bd917a09401ed44911b06f8cc2576b86dd488e2..74327aa7c7ec868d1f7b690abd1744cd6e528195 100644 (file)
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -1038,8 +1038,16 @@ sh_print_operand_address (FILE *stream, machine_mode /*mode*/, rtx x)
              int base_num = true_regnum (base);
              int index_num = true_regnum (index);
 
-             fprintf (stream, "@(r0,%s)",
-                      reg_names[MAX (base_num, index_num)]);
+             /* If base or index is R0, make sure that it comes first.
+                Usually one of them will be R0, but the order might be wrong.
+                If neither base nor index are R0 it's an error and we just
+                pass it on to the assembler.  This avoids silent wrong code
+                bugs.  */
+             if (base_num == 0 && index_num != 0)
+               std::swap (base_num, index_num);
+
+             fprintf (stream, "@(%s,%s)", reg_names[index_num],
+                                          reg_names[base_num]);
              break;
            }