Add copyright header, comment on cascade

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index 06ae3fc044e2e035bb9aae3867e0f876b84e8d4b..a8c2dcccc051bdb7767e481c4896238a047d342c 100644 (file)
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -1,7 +1,31 @@
-// From Eddie Hung\r
-// extracted from: https://github.com/eddiehung/vtr-with-yosys/blob/vtr7-with-yosys/vtr_flow/misc/yosys_models.v#L220\r
-// revised by Andre DeHon\r
-// further revised by David Shah\r
+/*\r
+ *  yosys -- Yosys Open SYnthesis Suite\r
+ *\r
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>\r
+ *                2019  Eddie Hung    <eddie@fpgeh.com>\r
+ *                2019  David Shah    <dave@ds0.me>\r
+ *\r
+ *  Permission to use, copy, modify, and/or distribute this software for any\r
+ *  purpose with or without fee is hereby granted, provided that the above\r
+ *  copyright notice and this permission notice appear in all copies.\r
+ *\r
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\r
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\r
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\r
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\r
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\r
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\r
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\r
+ *\r
+ *  ---\r
+ *\r
+ *  Tech-mapping rules for decomposing arbitrarily-sized $mul cells\r
+ *  into an equivalent collection of smaller `DSP_NAME cells (with the \r
+ *  same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached \r
+ *  to $shl and $add cells.\r
+ *\r
+ */\r
+\r
 `ifndef DSP_A_MAXWIDTH\r
 $error("Macro DSP_A_MAXWIDTH must be defined");\r
 `endif\r
@@ -125,6 +149,9 @@ module \$__mul (A, B, Y);
                                        .B(B),\r
                                        .Y(partial[i])\r
                                );\r
+                // TODO: Currently a 'cascade' approach to summing the partial \r
+                //       products is taken here, but a more efficient 'binary\r
+                //       reduction' approach also exists...\r
                                assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1];\r
                        end\r
 \r
@@ -182,6 +209,9 @@ module \$__mul (A, B, Y);
                                        .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}),\r
                                        .Y(partial[i])\r
                                );\r
+                // TODO: Currently a 'cascade' approach to summing the partial \r
+                //       products is taken here, but a more efficient 'binary\r
+                //       reduction' approach also exists...\r
                                assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[i-1];\r
                        end\r
 \r