(no commit message)

diff --git a/3d_gpu/layouts/coriolis2_180nm.mdwn b/3d_gpu/layouts/coriolis2_180nm.mdwn
index 694303e415ab44aa01b74aa0135fba62a98bc64c..aa3c7d88fe136c821402c094236a772ee10d0e7c 100644 (file)
--- a/3d_gpu/layouts/coriolis2_180nm.mdwn
+++ b/3d_gpu/layouts/coriolis2_180nm.mdwn
@@ -73,13 +73,13 @@ to ensure complete consistency across
 JTAG also contains a Wishbone Master for direct access to Memory
 and also a DMI Interface for controlling the core.  In simulations
 a JTAG client was implemented both in nmigen HDL as well as
-verilator.  The exact same openocd scripts and direct
+verilator.  The exact same openocd scripts or direct
 JTAG connectivity using jtagremote can then be used on:
 
 * nmigen HDL simulations
 * verilator simulations
-* FPGA
-* ls180 ASIC
+* [[HDL_workflow/ECP5_FPGA]]
+* the actual ls180 ASIC
 
 [[!img 180nm_Oct2020/ls180.svg size="400x" ]]