ARM: Implement the udiv instruction.

diff --git a/src/arch/arm/isa/formats/mult.isa b/src/arch/arm/isa/formats/mult.isa
index 8b3720e49f78a5ae179c2fec71e1244371ebfee2..cfd00b1a5cabeba4db93119942d3a0443e4fef40 100644 (file)
--- a/src/arch/arm/isa/formats/mult.isa
+++ b/src/arch/arm/isa/formats/mult.isa
@@ -303,7 +303,7 @@ def format Thumb32LongMulMulAccAndDiv() {{
             break;
           case 0x3:
             if (op2 == 0xf) {
-                return new WarnUnimplemented("udiv", machInst);
+                return new Udiv(machInst, rdhi, rn, rm);
             }
             break;
           case 0x4:

diff --git a/src/arch/arm/isa/insts/div.isa b/src/arch/arm/isa/insts/div.isa
index b3bd19cdb1fe637594b1a8218853f98b38d11d2f..b240e296790bd5ec852cd506d853a66cedf0c281 100644 (file)
--- a/src/arch/arm/isa/insts/div.isa
+++ b/src/arch/arm/isa/insts/div.isa
@@ -53,4 +53,18 @@ let {{
     header_output = RegRegRegOpDeclare.subst(sdivIop)
     decoder_output = RegRegRegOpConstructor.subst(sdivIop)
     exec_output = PredOpExecute.subst(sdivIop)
+
+    udivCode = '''
+    if (Op2.uw == 0) {
+        Dest.uw = 0;
+    } else {
+        Dest.uw = Op1.uw / Op2.uw;
+    }
+    '''
+    udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp",
+                            { "code": udivCode,
+                              "predicate_test": predicateTest }, [])
+    header_output += RegRegRegOpDeclare.subst(udivIop)
+    decoder_output += RegRegRegOpConstructor.subst(udivIop)
+    exec_output += PredOpExecute.subst(udivIop)
 }};