Refine macc testcase

diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v
index 9d684477fe63ac6f3b8c7ea983f9e55426b72920..e36b2bab1e5cf3bcee264fb3f9d8d63abbbebeb5 100644 (file)
--- a/tests/xilinx/macc.v
+++ b/tests/xilinx/macc.v
@@ -42,26 +42,29 @@ endmodule
 
 // Adapted variant of above
 module macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) (
-       input clk, ce, rst,
+       input clk,
+       input ce,
+       input rst,
        input signed [SIZEIN-1:0] a, b,
-       output signed [SIZEOUT-1:0] accum_out
+       output signed [SIZEOUT-1:0] accum_out,
+       output overflow
 );
 // Declare registers for intermediate values
 reg signed [SIZEIN-1:0] a_reg, b_reg, a_reg2, b_reg2;
-reg rst_reg;
-reg signed [2*SIZEIN-1:0] mult_reg;
-reg signed [SIZEOUT-1:0] adder_out, old_result;
+reg signed [2*SIZEIN-1:0] mult_reg = 0;
+reg signed [SIZEOUT:0] adder_out = 0;
+reg overflow_reg;
 always @(posedge clk) begin
-       if (ce)
+       //if (ce)
        begin
                a_reg <= a;
                b_reg <= b;
                a_reg2 <= a_reg;
                b_reg2 <= b_reg;
                mult_reg <= a_reg2 * b_reg2;
-               rst_reg <= rst;
                // Store accumulation result into a register
                adder_out <= adder_out + mult_reg;
+               overflow_reg <= overflow;
        end
        if (rst) begin
                a_reg <= 0;
@@ -70,10 +73,12 @@ always @(posedge clk) begin
                b_reg2 <= 0;
                mult_reg <= 0;
                adder_out <= 0;
+               overflow_reg <= 1'b0;
        end
 end
+assign overflow = (adder_out >= 2**(SIZEOUT-1)) | overflow_reg;
 
 // Output accumulation result
-assign accum_out = adder_out;
+assign accum_out = overflow ? 2**(SIZEOUT-1)-1 : adder_out;
 
 endmodule

diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys
index 294b83c69b41edfe8f520fa96501862e5df9af2c..417a3b21b7fe7a87dea21e8538b3d8f1a140cb14 100644 (file)
--- a/tests/xilinx/macc.ys
+++ b/tests/xilinx/macc.ys
@@ -25,4 +25,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd macc2 # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:DSP48E1
-select -assert-none t:BUFG t:DSP48E1 %% t:* %D
+select -assert-count 1 t:FDRE
+select -assert-count 1 t:LUT2
+select -assert-count 41 t:LUT3
+select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D