iris: Cross-link iris_batches so they can potentially flush each other

This makes e.g. the render batch aware of the compute batch, so it can
ask questions like "is this BO referenced by some other batch?" and do
something about that.

diff --git a/src/gallium/drivers/iris/iris_batch.c b/src/gallium/drivers/iris/iris_batch.c
index afc01109615df361142a12dc9c4718226453f298..8f53dacb9dde7a2202c0d71f93caecc1bdbaafc4 100644 (file)
--- a/src/gallium/drivers/iris/iris_batch.c
+++ b/src/gallium/drivers/iris/iris_batch.c
@@ -139,6 +139,7 @@ iris_init_batch(struct iris_batch *batch,
                 struct iris_screen *screen,
                 struct iris_vtable *vtbl,
                 struct pipe_debug_callback *dbg,
+                struct iris_batch **all_batches,
                 uint8_t engine)
 {
    batch->screen = screen;
@@ -161,6 +162,14 @@ iris_init_batch(struct iris_batch *batch,
                                                  _mesa_key_pointer_equal);
    batch->cache.depth = _mesa_set_create(NULL, _mesa_hash_pointer,
                                          _mesa_key_pointer_equal);
+
+   memset(batch->other_batches, 0, sizeof(batch->other_batches));
+
+   for (int i = 0, j = 0; i < IRIS_BATCH_COUNT; i++) {
+      if (all_batches[i] != batch)
+         batch->other_batches[j++] = all_batches[i];
+   }
+
    if (unlikely(INTEL_DEBUG)) {
       batch->state_sizes =
          _mesa_hash_table_create(NULL, uint_key_hash, uint_key_compare);

diff --git a/src/gallium/drivers/iris/iris_batch.h b/src/gallium/drivers/iris/iris_batch.h
index 8ff3f60fa9d2fe544913c36dd002a3956b393009..17f2a581d9758d3f612278ebbf67eaf166ac8990 100644 (file)
--- a/src/gallium/drivers/iris/iris_batch.h
+++ b/src/gallium/drivers/iris/iris_batch.h
@@ -36,6 +36,8 @@
 /* Our target batch size - flush approximately at this point. */
 #define BATCH_SZ (20 * 1024)
 
+#define IRIS_BATCH_COUNT 2
+
 struct iris_address {
    struct iris_bo *bo;
    uint64_t offset;
@@ -74,6 +76,9 @@ struct iris_batch {
    /** The amount of aperture space (in bytes) used by all exec_bos */
    int aperture_space;
 
+   /** List of other batches which we might need to flush to use a BO */
+   struct iris_batch *other_batches[IRIS_BATCH_COUNT - 1];
+
    struct {
       /**
        * Set of struct brw_bo * that have been rendered to within this
@@ -103,6 +108,7 @@ void iris_init_batch(struct iris_batch *batch,
                      struct iris_screen *screen,
                      struct iris_vtable *vtbl,
                      struct pipe_debug_callback *dbg,
+                     struct iris_batch **other_batches,
                      uint8_t ring);
 void iris_chain_to_new_batch(struct iris_batch *batch);
 void iris_batch_free(struct iris_batch *batch);

diff --git a/src/gallium/drivers/iris/iris_context.c b/src/gallium/drivers/iris/iris_context.c
index 14c5d1dbad968000083708be144aaeab54491c93..890505421fa646a86cbe61ba47014d0a03b13366 100644 (file)
--- a/src/gallium/drivers/iris/iris_context.c
+++ b/src/gallium/drivers/iris/iris_context.c
@@ -209,6 +209,17 @@ iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
 
    genX_call(devinfo, init_state, ice);
    genX_call(devinfo, init_blorp, ice);
+
+   struct iris_batch *batches[IRIS_BATCH_COUNT] = {
+      &ice->render_batch,
+      &ice->compute_batch,
+   };
+
+   for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
+      iris_init_batch(batches[i], screen, &ice->vtbl, &ice->dbg,
+                      batches, I915_EXEC_RENDER);
+   }
+
    ice->vtbl.init_render_context(screen, &ice->render_batch, &ice->vtbl,
                                  &ice->dbg);
    ice->vtbl.init_compute_context(screen, &ice->compute_batch, &ice->vtbl,

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index c0173e45d96d48f8e785b0ae43260a605c070895..3c668cac980e67194723a5b3f6ea0989b541af0a 100644 (file)
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -611,8 +611,6 @@ iris_init_render_context(struct iris_screen *screen,
    UNUSED const struct gen_device_info *devinfo = &screen->devinfo;
    uint32_t reg_val;
 
-   iris_init_batch(batch, screen, vtbl, dbg, I915_EXEC_RENDER);
-
    emit_pipeline_select(batch, _3D);
 
    init_state_base_address(batch);
@@ -698,8 +696,6 @@ iris_init_compute_context(struct iris_screen *screen,
 {
    UNUSED const struct gen_device_info *devinfo = &screen->devinfo;
 
-   iris_init_batch(batch, screen, vtbl, dbg, I915_EXEC_RENDER);
-
    emit_pipeline_select(batch, GPGPU);
 
    init_state_base_address(batch);