add L2 cache size in identifier + function to flush L2

diff --git a/misoclib/identifier/__init__.py b/misoclib/identifier/__init__.py
index 117219d1b6ee0ffacd57910e677507d9bf2a7736..c8ebdb3c3a1663d51223b166dfa025c95ee3668a 100644 (file)
--- a/misoclib/identifier/__init__.py
+++ b/misoclib/identifier/__init__.py
@@ -4,10 +4,11 @@ from migen.bank.description import *
 from misoclib.identifier import git
 
 class Identifier(Module, AutoCSR):
-       def __init__(self, sysid, frequency, revision=None):
+       def __init__(self, sysid, frequency, l2_size, revision=None):
                self._r_sysid = CSRStatus(16)
                self._r_revision = CSRStatus(32)
                self._r_frequency = CSRStatus(32)
+               self._r_l2_size = CSRStatus(8)
                
                ###
 
@@ -17,5 +18,6 @@ class Identifier(Module, AutoCSR):
                self.comb += [
                        self._r_sysid.status.eq(sysid),
                        self._r_revision.status.eq(revision),
-                       self._r_frequency.status.eq(frequency)
+                       self._r_frequency.status.eq(frequency),
+                       self._r_l2_size.status.eq(l2_size)
                ]

diff --git a/software/include/base/system.h b/software/include/base/system.h
index 7ec2cdedf72237d6ee8025c0b1e18d804cd6dbcb..41be80affde8b36916150b80a41f22c037db9ef4 100644 (file)
--- a/software/include/base/system.h
+++ b/software/include/base/system.h
@@ -7,6 +7,7 @@ extern "C" {
 
 void flush_cpu_icache(void);
 void flush_cpu_dcache(void);
+void flush_l2_cache(void);
 
 #ifdef __cplusplus
 }

diff --git a/software/libbase/system.c b/software/libbase/system.c
index 41a30395734a867ef38d576f8a3458ca174ac381..fcb585d973aafe1c514a8703deaa088eed245871 100644 (file)
--- a/software/libbase/system.c
+++ b/software/libbase/system.c
@@ -2,6 +2,8 @@
 #include <uart.h>
 
 #include <system.h>
+#include <hw/mem.h>
+#include <hw/csr.h>
 
 void flush_cpu_icache(void)
 {
@@ -21,3 +23,17 @@ void flush_cpu_dcache(void)
                "nop\n"
        );
 }
+
+void flush_l2_cache(void)
+{
+       unsigned int l2_nwords;
+       unsigned int i;
+       register unsigned int addr;
+       register unsigned int dummy;
+
+       l2_nwords = 1 << (identifier_l2_size_read() - 2);
+       for(i=0;i<2*l2_nwords;i++) {
+               addr = SDRAM_BASE + i*4;
+               __asm__ volatile("lw %0, (%1+0)\n":"=r"(dummy):"r"(addr));
+       }
+}

diff --git a/top.py b/top.py
index f73bd8f63397e75cf6623cc9297b9f121323f6b8..321b87c8929adc1e941c0197e6d48a754c871ecc 100644 (file)
--- a/top.py
+++ b/top.py
@@ -158,7 +158,8 @@ class SoC(Module):
                #
                self.submodules.crg = mxcrg.MXCRG(MXClockPads(platform), clk_freq)
                self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
-               self.submodules.identifier = identifier.Identifier(self.known_platform_id[platform_name], int(clk_freq))
+               self.submodules.identifier = identifier.Identifier(self.known_platform_id[platform_name], int(clk_freq),
+                       log2_int(l2_size))
                self.submodules.timer0 = timer.Timer()
                if platform_name == "mixxeo":
                        self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))