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-
 # Note about naming
 
 the original assessment for SVP from 18 months ago concluded that it should be easy for scalar (non SV) instructions to get at the exact same scalar registers when in SVP mode.  otherwise scalar v3.0B code needs to restrict itself to a massively truncated subset of the scalar registers numbered 0-31 (only r0, r4, r8...) which hugely interferes with ABIs to such an extent that it would compromise SV.
@@ -204,3 +203,33 @@ Evaluation:
 * CR ops: maybe on mvs, not on arithmetic.
 
 therefore it makes no sense to have DEST SUBVL, and instead to have special mv operations.  see [[mv.vec]]
+
+# SVP64Single review
+
+full review needed, answering question:
+
+    if sv.op RT.scalar RA.scalar RB.scalar is set to "VL=1" is anything lost?
+
+four aspects:
+
+1) instructions with only one source
+
+2) RM Modes
+
+3) is the loss of the dynamic meaning "VL=0" nop effect important?
+
+4) why would "sv.op all-scalar" be inside a loop in the first place?
+
+## answers to 2, RM Modes
+
+Normal Mode:
+
+* simple mode is straight vectorisation.
+* reduce mode
+* ffirst or data-dependent fail-on-first: 
+* sat mode or saturation:
+* pred-result mode
+
+simple mode is fine including on predication but has a CHANGE OF BEHAVIOUR. first bit of src/dest is used when zeroing is on, but first ENABLED bit of predicate is used when VL>1.
+
+reduce mode is unaffected (meaningless)