Always generate if no match

diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg
index e8288c54ac30fc09b2b3af4c14b7a55e01a384ac..bdb59c2f76b0aac98ba7b862a90db98824a49975 100644 (file)
--- a/passes/pmgen/xilinx_srl.pmg
+++ b/passes/pmgen/xilinx_srl.pmg
@@ -142,7 +142,7 @@ match next
        filter !next->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || (next->hasParam(\IS_D_INVERTED) && param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool())
        filter !next->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || (next->hasParam(\IS_R_INVERTED) && param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool())
        filter !next->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R)
-generate 10
+generate
        Cell *cell = module->addCell(NEW_ID, chain.back()->type);
        cell->setPort(\C, chain.back()->getPort(\C));
        cell->setPort(\D, module->addWire(NEW_ID));