Another small freduce cleanup/bugfix

diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index cc3739fe42c7e53207861d7bff02080f41513a16..4db11436e2a24afeecf86625d49178ca13aefa36 100644 (file)
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -482,7 +482,8 @@ struct FreduceWorker
                                RTLIL::Cell *drv = drivers.at(grp[i].bit).first;
                                RTLIL::Wire *dummy_wire = module->new_wire(1, NEW_ID);
                                for (auto &port : drv->connections)
-                                       sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);
+                                       if (ct.cell_output(drv->type, port.first))
+                                               sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);
 
                                if (grp[i].inverted)
                                {