def setupBootLoader(self, cur_sys, loc):
if not cur_sys.boot_loader:
- cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ]
+ cur_sys.boot_loader = [ loc('boot.arm64'), loc('boot.arm') ]
cur_sys.atags_addr = 0x8000000
cur_sys.load_offset = 0x80000000
]
def setupBootLoader(self, cur_sys, loc):
- cur_sys.boot_loader = [ loc('boot_emm_v2.arm64') ]
+ cur_sys.boot_loader = [ loc('boot_v2.arm64') ]
super(VExpress_GEM5_V2_Base,self).setupBootLoader(
cur_sys, loc)
ARM-specific create_system method to a class deriving from one of
the generic base systems.
"""
- def __init__(self, machine_type, **kwargs):
+ def __init__(self, machine_type, aarch64_kernel, **kwargs):
"""
Arguments:
machine_type -- String describing the platform to simulate
self.num_cpus = kwargs.get('num_cpus', 1)
self.mem_size = kwargs.get('mem_size', '256MB')
self.use_ruby = kwargs.get('use_ruby', False)
+ self.aarch64_kernel = aarch64_kernel
def create_system(self):
- sc = SysConfig(None, self.mem_size, None)
+ if self.aarch64_kernel:
+ gem5_kernel = "vmlinux.arm64"
+ disk_image = "m5_exit.squashfs.arm64"
+ else:
+ gem5_kernel = "vmlinux.arm"
+ disk_image = "m5_exit.squashfs.arm"
+
+ default_kernels = {
+ "VExpress_GEM5_V1": gem5_kernel,
+ }
+
+ sc = SysConfig(None, self.mem_size, disk_image, "/dev/sda")
system = FSConfig.makeArmSystem(self.mem_mode,
self.machine_type, self.num_cpus,
sc, False, ruby=self.use_ruby)
system.panic_on_panic = True
system.panic_on_oops = True
- default_kernels = {
- "VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5",
- "VExpress_EMM64": "vmlinux.aarch64.20140821",
- }
system.kernel = SysPaths.binary(default_kernels[self.machine_type])
- default_dtbs = {
- "VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.{}cpu.dtb" \
- .format(self.num_cpus),
- "VExpress_EMM64": "vexpress.aarch64.20140821.dtb",
- }
- system.dtb_filename = SysPaths.binary(default_dtbs[self.machine_type])
self.init_system(system)
+
+ system.generateDtb(m5.options.outdir, 'system.dtb')
return system
class LinuxArmFSSystem(LinuxArmSystemBuilder,
BaseFSSystem):
"""Basic ARM full system builder."""
- def __init__(self, machine_type='VExpress_EMM', **kwargs):
+ def __init__(self,
+ machine_type='VExpress_GEM5_V1',
+ aarch64_kernel=True,
+ **kwargs):
"""Initialize an ARM system that supports full system simulation.
Note: Keyword arguments that are not listed below will be
machine_type -- String describing the platform to simulate
"""
BaseFSSystem.__init__(self, **kwargs)
- LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs)
+ LinuxArmSystemBuilder.__init__(
+ self, machine_type, aarch64_kernel, **kwargs)
def create_caches_private(self, cpu):
# Use the more representative cache configuration
test cases.
"""
- def __init__(self, machine_type='VExpress_EMM', **kwargs):
+ def __init__(self,
+ machine_type='VExpress_GEM5_V1',
+ aarch64_kernel=True,
+ **kwargs):
BaseFSSystemUniprocessor.__init__(self, **kwargs)
- LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs)
+ LinuxArmSystemBuilder.__init__(
+ self, machine_type, aarch64_kernel, **kwargs)
class LinuxArmFSSwitcheroo(LinuxArmSystemBuilder, BaseFSSwitcheroo):
"""Uniprocessor ARM system prepared for CPU switching"""
- def __init__(self, machine_type='VExpress_EMM', **kwargs):
+ def __init__(self,
+ machine_type='VExpress_GEM5_V1',
+ aarch64_kernel=True,
+ **kwargs):
BaseFSSwitcheroo.__init__(self, **kwargs)
- LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs)
+ LinuxArmSystemBuilder.__init__(
+ self, machine_type, aarch64_kernel, **kwargs)
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystem(mem_mode='timing',
+root = LinuxArmFSSystem(aarch64_kernel=False,
+ mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU,
num_cpus=2).create_root()
-# Copyright (c) 2014 ARM Limited
+# Copyright (c) 2014, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
+root = LinuxArmFSSystemUniprocessor(aarch64_kernel=False,
+ mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU).create_root()
-# Copyright (c) 2012, 2017 ARM Limited
+# Copyright (c) 2012, 2017, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from arm_generic import *
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
-root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
+root = LinuxArmFSSystemUniprocessor(aarch64_kernel=False,
+ mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3,
checker=True).create_root()
-# Copyright (c) 2012, 2017 ARM Limited
+# Copyright (c) 2012, 2017, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from arm_generic import *
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
-root = LinuxArmFSSystem(mem_mode='timing',
+root = LinuxArmFSSystem(aarch64_kernel=False,
+ mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3,
num_cpus=2).create_root()
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from arm_generic import *
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
-root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
+root = LinuxArmFSSystemUniprocessor(aarch64_kernel=False,
+ mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3).create_root()
-# Copyright (c) 2015 ARM Limited
+# Copyright (c) 2015, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from arm_generic import *
import checkpoint
-root = LinuxArmFSSystemUniprocessor(mem_mode='atomic',
+root = LinuxArmFSSystemUniprocessor(aarch64_kernel=False,
+ mem_mode='atomic',
mem_class=SimpleMemory,
cpu_class=AtomicSimpleCPU).create_root()
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystem(mem_mode='atomic',
+root = LinuxArmFSSystem(aarch64_kernel=False,
+ mem_mode='atomic',
mem_class=SimpleMemory,
cpu_class=AtomicSimpleCPU,
num_cpus=2).create_root()
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystemUniprocessor(mem_mode='atomic',
+root = LinuxArmFSSystemUniprocessor(aarch64_kernel=False,
+ mem_mode='atomic',
mem_class=SimpleMemory,
cpu_class=AtomicSimpleCPU).create_root()
-# Copyright (c) 2017 ARM Limited
+# Copyright (c) 2017, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystem(mem_mode='timing',
+root = LinuxArmFSSystem(aarch64_kernel=False,
+ mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU,
num_cpus=2,
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystem(mem_mode='timing',
+root = LinuxArmFSSystem(aarch64_kernel=False,
+ mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU,
num_cpus=2).create_root()
-# Copyright (c) 2017 ARM Limited
+# Copyright (c) 2017, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
+root = LinuxArmFSSystemUniprocessor(aarch64_kernel=False,
+ mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU,
use_ruby=True).create_root()
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
+root = LinuxArmFSSystemUniprocessor(aarch64_kernel=False,
+ mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU).create_root()
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
import switcheroo
root = LinuxArmFSSwitcheroo(
+ aarch64_kernel=False,
mem_class=DDR3_1600_8x8,
cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, MinorCPU, DerivO3CPU)
).create_root()
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
import switcheroo
root = LinuxArmFSSwitcheroo(
+ aarch64_kernel=False,
mem_class=DDR3_1600_8x8,
cpu_classes=(DerivO3CPU, DerivO3CPU)
).create_root()
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystem(machine_type='VExpress_EMM64',
- mem_mode='timing',
+root = LinuxArmFSSystem(mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU,
num_cpus=2).create_root()
-# Copyright (c) 2014 ARM Limited
+# Copyright (c) 2014, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
- mem_mode='timing',
+root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU).create_root()
-# Copyright (c) 2012, 2017 ARM Limited
+# Copyright (c) 2012, 2017, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from arm_generic import *
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
-root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
- mem_mode='timing',
+root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3,
checker=True).create_root()
-# Copyright (c) 2012, 2017 ARM Limited
+# Copyright (c) 2012, 2017, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from arm_generic import *
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
-root = LinuxArmFSSystem(machine_type='VExpress_EMM64',
- mem_mode='timing',
+root = LinuxArmFSSystem(mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3,
num_cpus=2).create_root()
-# Copyright (c) 2012, 2017 ARM Limited
+# Copyright (c) 2012, 2017, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from arm_generic import *
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
-root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
- mem_mode='timing',
+root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3).create_root()
-# Copyright (c) 2015 ARM Limited
+# Copyright (c) 2015, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from arm_generic import *
import checkpoint
-root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
- mem_mode='atomic',
+root = LinuxArmFSSystemUniprocessor(mem_mode='atomic',
mem_class=SimpleMemory,
cpu_class=AtomicSimpleCPU).create_root()
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystem(machine_type='VExpress_EMM64',
- mem_mode='atomic',
+root = LinuxArmFSSystem(mem_mode='atomic',
mem_class=SimpleMemory,
cpu_class=AtomicSimpleCPU,
num_cpus=2).create_root()
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
- mem_mode='atomic',
+root = LinuxArmFSSystemUniprocessor(mem_mode='atomic',
mem_class=SimpleMemory,
cpu_class=AtomicSimpleCPU).create_root()
-# Copyright (c) 2017 ARM Limited
+# Copyright (c) 2017, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystem(machine_type='VExpress_EMM64',
- mem_mode='timing',
+root = LinuxArmFSSystem(mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU,
num_cpus=2,
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystem(machine_type='VExpress_EMM64',
- mem_mode='timing',
+root = LinuxArmFSSystem(mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU,
num_cpus=2).create_root()
-# Copyright (c) 2017 ARM Limited
+# Copyright (c) 2017, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
- mem_mode='timing',
+root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU,
use_ruby=True).create_root()
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
- mem_mode='timing',
+root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU).create_root()
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
import switcheroo
root = LinuxArmFSSwitcheroo(
- machine_type='VExpress_EMM64',
mem_class=SimpleMemory,
cpu_classes=(AtomicSimpleCPU, AtomicSimpleCPU)
).create_root()
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
import switcheroo
root = LinuxArmFSSwitcheroo(
- machine_type='VExpress_EMM64',
mem_class=DDR3_1600_8x8,
cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, MinorCPU, DerivO3CPU)
).create_root()
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
import switcheroo
root = LinuxArmFSSwitcheroo(
- machine_type='VExpress_EMM64',
mem_class=DDR3_1600_8x8,
cpu_classes=(DerivO3CPU, DerivO3CPU)
).create_root()
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
import switcheroo
root = LinuxArmFSSwitcheroo(
- machine_type='VExpress_EMM64',
mem_class=DDR3_1600_8x8,
cpu_classes=(TimingSimpleCPU, TimingSimpleCPU)
).create_root()
'realview64-simple-timing-dual-ruby',
]
-tarball = 'aarch-system-2014-10.tar.bz2'
+tarball = 'aarch-system-201901106.tar.bz2'
url = "http://gem5.org/dist/current/arm/" + tarball
path = os.path.dirname(os.path.abspath(__file__))
arm_fs_binaries = DownloadedArchive(url, path, tarball)