back.rtlil: give clocks and resets nicer names.

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 808ae32e3f5520b72c03ec9af3aa367296b57cf6..0bd69f311304a2d5aad09db7b82bd4020758937d 100644 (file)
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -400,6 +400,13 @@ def convert_fragment(builder, fragment, name, clock_domains):
         for signal in fragment.ports:
             xformer.add_port(signal)
 
+        # Make sure clocks and resets get sensible names, by eagerly converting them outside
+        # of any hierarchy.
+        for cd_name, _ in fragment.iter_sync():
+            cd = clock_domains[cd_name]
+            xformer(cd.clk)
+            xformer(cd.reset)
+
         for subfragment, sub_name in fragment.subfragments:
             sub_name, sub_port_map = \
                 convert_fragment(builder, subfragment, sub_name, clock_domains)