m68hc11.md ("bitcmpqi"): New pattern for bitb instruction.

	* config/m68hc11/m68hc11.md ("bitcmpqi"): New pattern for bitb
	instruction.
	("bitcmpqi2"): New pattern for bit-extract and test.
	("bitcmphi"): New pattern for bitb/bita instructions.

From-SVN: r41812

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d752c5666679eb0a9e8a2c42f88173776fb3c1f7..9c9e4ca724c33f02a2bac9912c0d76c81ed9b24d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2001-05-03  Stephane Carrez  <Stephane.Carrez@worldnet.fr>
+
+       * config/m68hc11/m68hc11.md ("bitcmpqi"): New pattern for bitb
+       instruction.
+       ("bitcmpqi2"): New pattern for bit-extract and test.
+       ("bitcmphi"): New pattern for bitb/bita instructions.
+
 2001-05-03  Joseph S. Myers  <jsm28@cam.ac.uk>
 
        * gccbug.in: Use a temporary directory when the mktemp command is

diff --git a/gcc/config/m68hc11/m68hc11.md b/gcc/config/m68hc11/m68hc11.md
index ec6956eafb505e3958f0c51c3b8a3322ea56a837..a4380c32aa4cb51578c625274796cb070898c7fb 100644 (file)
--- a/gcc/config/m68hc11/m68hc11.md
+++ b/gcc/config/m68hc11/m68hc11.md
@@ -383,6 +383,87 @@
   DONE;
 }")
 
+(define_insn "bitcmpqi"
+  [(set (cc0)
+       (and:QI (match_operand:QI 0 "tst_operand" "d,d,d")
+               (match_operand:QI 1 "cmp_operand" "im,*A,u")))]
+  ""
+  "@
+   bitb\\t%1
+   #
+   bitb\\t%1")
+
+(define_insn "bitcmpqi_z_used"
+  [(set (cc0)
+       (and:QI (match_operand:QI 0 "tst_operand" "d")
+               (match_operand:QI 1 "cmp_operand" "m")))
+   (use (match_operand:HI 2 "hard_reg_operand" "xy"))
+   (use (reg:HI 11))]
+  ""
+  "#")
+  
+(define_split /* "bitcmpqi_z_used" */
+  [(set (cc0)
+       (and:QI (match_operand:QI 0 "tst_operand" "d")
+               (match_operand:QI 1 "cmp_operand" "m")))
+   (use (match_operand:HI 2 "hard_reg_operand" "xy"))
+   (use (reg:HI 11))]
+  "z_replacement_completed == 2"
+  [(set (mem:HI (pre_dec:HI (reg:HI 3))) (match_dup 2))
+   (set (match_dup 2) (match_dup 3))
+   (set (cc0) (and:QI (match_dup 0) (match_dup 1)))
+   (set (match_dup 2) (mem:HI (post_inc:HI (reg:HI 3))))]
+  "operands[3] = gen_rtx (REG, HImode, SOFT_Z_REGNUM);")
+
+(define_insn "bitcmphi"
+  [(set (cc0)
+       (and:HI (match_operand:HI 0 "tst_operand" "d")
+               (match_operand:HI 1 "const_int_operand" "i")))]
+  "(INTVAL (operands[1]) & 0x0ff) == 0
+   || (INTVAL (operands[1]) & 0x0ff00) == 0"
+  "*
+{
+   if ((INTVAL (operands[1]) & 0x0ff) == 0)
+     return \"bita\\t%h1\";
+   else
+     return \"bitb\\t%1\";
+}")
+
+(define_insn "bitcmpqi_12"
+  [(set (cc0)
+       (zero_extract (match_operand:HI 0 "tst_operand" "d")
+                     (match_operand:HI 1 "const_int_operand" "i")
+                     (match_operand:HI 2 "const_int_operand" "i")))]
+  "(unsigned) (INTVAL (operands[2]) + INTVAL (operands[1])) <= 8
+   || (((unsigned) (INTVAL (operands[2]) + INTVAL (operands[1])) <= 16)
+       && (unsigned) INTVAL (operands[2]) >= 8)"
+  "*
+{
+   rtx ops[1];
+   int mask;
+   int startpos = INTVAL (operands[2]);
+   int bitsize = INTVAL (operands[1]);
+
+   if (startpos >= 8)
+     {
+       startpos -= 8;
+       mask = (1 << (startpos + bitsize)) - 1;
+       mask &= ~((1 << startpos) - 1);
+
+       ops[0] = GEN_INT (mask);
+       output_asm_insn (\"bita\\t%0\", ops);
+     }
+   else
+     {
+       mask = (1 << (startpos + bitsize)) - 1;
+       mask &= ~((1 << startpos) - 1);
+
+       ops[0] = GEN_INT (mask);
+       output_asm_insn (\"bitb\\t%0\", ops);
+     }
+   return \"\";
+}")
+
 (define_insn "cmpqi_1"
   [(set (cc0)
        (compare (match_operand:QI 0 "tst_operand" "d,d,*x*y,*x*y")