2015-09-26 Jeff Law <law@redhat.com>
+ * config/arc/arc.c (arc_output_addsi): Fix left shift undefined
+ behaviour.
+ * config/arc/constraints.md (Cca, C2a): Fix left shift undefined
+ behaviour.
+
* config/sh/sh.h (CONST_OK_FOR_J16): Fix left shift undefined
behaviour
int range_factor = neg_intval & intval;
int shift;
- if (intval == -1 << 31)
+ if (intval == (HOST_WIDE_INT) (HOST_WIDE_INT_M1U << 31))
ADDSI_OUTPUT1 ("bxor%? %0,%1,31");
/* If we can use a straight add / sub instead of a {add,sub}[123] of
if ((scale-1) & offset)
scale = 1;
shift = scale >> 1;
- offset_base = (offset + (256 << shift)) & (-512 << shift);
+ offset_base
+ = ((offset + (256 << shift))
+ & ((HOST_WIDE_INT)(-512U << shift)));
/* Sometimes the normal form does not suit DImode. We
could avoid that by using smaller ranges, but that
would give less optimized code when SImode is
"@internal
Conditional or three-address add / sub constant"
(and (match_code "const_int")
- (match_test "ival == -1 << 31
+ (match_test "ival == (HOST_WIDE_INT)(HOST_WIDE_INT_M1U << 31)
|| (ival >= -0x1f8 && ival <= 0x1f8
&& ((ival >= 0 ? ival : -ival)
<= 0x3f * (ival & -ival)))")))
"@internal
Unconditional two-address add / sub constant"
(and (match_code "const_int")
- (match_test "ival == -1 << 31
+ (match_test "ival == HOST_WIDE_INT (HOST_WIDE_INT_M1U << 31)
|| (ival >= -0x4000 && ival <= 0x4000
&& ((ival >= 0 ? ival : -ival)
<= 0x7ff * (ival & -ival)))")))