Fix broken abc9.v test due to inout being 1'bx

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 42f54209bc335398806b71a6218d8f1e6f5327da..f0a9ccdb96741b67654c3feac35a240427dde2c0 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -75,6 +75,7 @@ struct XAigerWriter
        dict<SigBit, int> ordered_outputs;
 
        vector<Cell*> box_list;
+       bool omode = false;
 
        int mkgate(int a0, int a1)
        {
@@ -409,9 +410,9 @@ struct XAigerWriter
                        // If encountering an inout port, or a keep-ed wire, then create a new wire
                        // with $inout.out suffix, make it a PO driven by the existing inout, and
                        // inherit existing inout's drivers
-                       if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
+                       if ((wire->port_input && wire->port_output && output_bits.count(bit) && !undriven_bits.count(bit))
                                        || wire->attributes.count("\\keep")) {
-                               log_assert(input_bits.count(bit) && output_bits.count(bit));
+                               log_assert(output_bits.count(bit));
                                RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
                                RTLIL::Wire *new_wire = module->wire(wire_name);
                                if (!new_wire)
@@ -486,6 +487,12 @@ struct XAigerWriter
                        ordered_outputs[bit] = aig_o++;
                        aig_outputs.push_back(bit2aig(bit));
                }
+
+               if (output_bits.empty()) {
+                       aig_o++;
+                       aig_outputs.push_back(0);
+                       omode = true;
+               }
        }
 
        void write_aiger(std::ostream &f, bool ascii_mode)
@@ -741,6 +748,8 @@ struct XAigerWriter
                for (auto &it : output_lines)
                        f << it.second;
                log_assert(output_lines.size() == output_bits.size());
+               if (omode && output_bits.empty())
+                       f << "output " << output_lines.size() << " 0 $__dummy__\n";
 
                wire_lines.sort();
                for (auto &it : wire_lines)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 1235af142c4410b5d1e3d905868fb1a2340be0f7..d50a38b7a2152d952fcfe2e2e8a9b2da86a44930 100644 (file)
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -836,6 +836,10 @@ void AigerReader::post_process()
                                RTLIL::Wire* wire = outputs[variable + co_count];
                                log_assert(wire);
                                log_assert(wire->port_output);
+                               if (escaped_s == "$__dummy__") {
+                                       wire->port_output = false;
+                                       continue;
+                               }
 
                                if (index == 0) {
                                        // Cope with the fact that a CO might be identical
@@ -945,12 +949,15 @@ void AigerReader::post_process()
                                other_wire->port_input = false;
                                other_wire->port_output = false;
                        }
-                       if (wire->port_input && other_wire)
-                               module->connect(other_wire, SigSpec(wire, i));
-                       else
+                       if (wire->port_input) {
+                               if (other_wire)
+                                       module->connect(other_wire, SigSpec(wire, i));
+                       }
+                       else {
                                                                  // Since we skip POs that are connected to Sx,
                                                                  // re-connect them here
                                module->connect(SigSpec(wire, i), other_wire ? other_wire : SigSpec(RTLIL::Sx));
+                       }
                }
        }