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radeon/llvm: Add i1 registers for SI.
authorTom Stellard <thomas.stellard@amd.com>
Wed, 25 Jul 2012 12:27:50 +0000 (08:27 -0400)
committerTom Stellard <thomas.stellard@amd.com>
Fri, 27 Jul 2012 17:08:08 +0000 (17:08 +0000)
src/gallium/drivers/radeon/SIISelLowering.cpp patch | blob | history

diff --git a/src/gallium/drivers/radeon/SIISelLowering.cpp b/src/gallium/drivers/radeon/SIISelLowering.cpp
index 7940085147020bce76bf5b2c1c4102a71dd7d34b..23eb4f8e23942c77f0c67e5b4dd2c90cc54f78a9 100644 (file)
--- a/src/gallium/drivers/radeon/SIISelLowering.cpp
+++ b/src/gallium/drivers/radeon/SIISelLowering.cpp
@@ -27,6 +27,8 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
   addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
   addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass);
   addRegisterClass(MVT::i64, &AMDGPU::VReg_64RegClass);
+  addRegisterClass(MVT::i1, &AMDGPU::SCCRegRegClass);
+  addRegisterClass(MVT::i1, &AMDGPU::VCCRegRegClass);
 
   addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
   addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);