[sim,xcc] add rdcycle/rdtime/rdinstret

diff --git a/riscv/insns/rdcycle.h b/riscv/insns/rdcycle.h
index 96f2a74050d7b3b4326f95f2a0327f748ff0dd61..9b966a683554407e2ddb44448101f2721e63e72e 100644 (file)
--- a/riscv/insns/rdcycle.h
+++ b/riscv/insns/rdcycle.h
@@ -1 +1 @@
-throw trap_illegal_instruction;
+RD = cycle;

diff --git a/riscv/insns/rdinstret.h b/riscv/insns/rdinstret.h
index 96f2a74050d7b3b4326f95f2a0327f748ff0dd61..9b966a683554407e2ddb44448101f2721e63e72e 100644 (file)
--- a/riscv/insns/rdinstret.h
+++ b/riscv/insns/rdinstret.h
@@ -1 +1 @@
-throw trap_illegal_instruction;
+RD = cycle;

diff --git a/riscv/insns/rdtime.h b/riscv/insns/rdtime.h
index 96f2a74050d7b3b4326f95f2a0327f748ff0dd61..9b966a683554407e2ddb44448101f2721e63e72e 100644 (file)
--- a/riscv/insns/rdtime.h
+++ b/riscv/insns/rdtime.h
@@ -1 +1 @@
-throw trap_illegal_instruction;
+RD = cycle;

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 0bab83ac643dac0e635a5a86249bcc8ba5ab2da2..4e06da48b809ee972efd3b9fb956f89e01c1b56a 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -28,11 +28,10 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   fromhost = 0;
   count = 0;
   compare = 0;
+  cycle = 0;
   set_sr(SR_S | SR_SX);  // SX ignored if 64b mode not supported
   set_fsr(0);
 
-  memset(counters,0,sizeof(counters));
-
   // vector stuff
   vecbanks = 0xff;
   vecbanks_count = 8;
@@ -175,6 +174,7 @@ void processor_t::step(size_t n, bool noisy)
 
       if(count++ == compare)
         cause |= 1 << (TIMER_IRQ+CAUSE_IP_SHIFT);
+      cycle++;
     }
     return;
   }

diff --git a/riscv/processor.h b/riscv/processor.h
index 7a09edf72db1fbfb536eae3a6155acb8c30ea6f7..1f458d584ba707763bb1eb41ef56297d1974bc78 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -51,7 +51,7 @@ private:
   mmu_t mmu;
 
   // counters
-  reg_t counters[32];
+  reg_t cycle;
 
   // functions
   void set_sr(uint32_t val);