Support setting ISA/subsets with --isa flag

Default is RV64IMAFDC.  Can do things like

  --isa=RV32 (which implies IMAFDC)
  --isa=IM (which implies RV64)
  --isa=RV64IMAFDXhwacha

diff --git a/config.h.in b/config.h.in
index 5293fa8dafc9121be87a0d46ab089f0402964547..f5608c59388be1b9f9acd47a73b5c07c6a05446b 100644 (file)
--- a/config.h.in
+++ b/config.h.in
@@ -33,21 +33,12 @@
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
 #undef RISCV_ENABLED
 
-/* Define if 64-bit mode is supported */
-#undef RISCV_ENABLE_64BIT
-
 /* Enable commit log generation */
 #undef RISCV_ENABLE_COMMITLOG
 
-/* Define if floating-point instructions are supported */
-#undef RISCV_ENABLE_FPU
-
 /* Enable PC histogram generation */
 #undef RISCV_ENABLE_HISTOGRAM
 
-/* Define if RISC-V Compressed is supported */
-#undef RISCV_ENABLE_RVC
-
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
 #undef SOFTFLOAT_ENABLED
 

diff --git a/configure b/configure
index bed5307c44d54087f1411f7b8a559ccbe0229b3b..5db4d53ede0c8fbbb96cc6a5379f92bfc49365c9 100755 (executable)
--- a/configure
+++ b/configure
@@ -664,9 +664,6 @@ enable_option_checking
 enable_stow
 enable_optional_subprojects
 with_fesvr
-enable_fpu
-enable_rvc
-enable_64bit
 enable_commitlog
 enable_histogram
 '
@@ -1300,9 +1297,6 @@ Optional Features:
   --enable-stow           Enable stow-based install
   --enable-optional-subprojects
                           Enable all optional subprojects
-  --disable-fpu           Disable floating-point
-  --disable-rvc           Disable RISC-V Compressed
-  --disable-64bit         Disable 64-bit mode
   --enable-commitlog      Enable commit log generation
   --enable-histogram      Enable PC histogram generation
 
@@ -3979,6 +3973,67 @@ ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ex
 ac_compiler_gnu=$ac_cv_cxx_compiler_gnu
 
 
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing dlopen" >&5
+$as_echo_n "checking for library containing dlopen... " >&6; }
+if ${ac_cv_search_dlopen+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  ac_func_search_save_LIBS=$LIBS
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+/* Override any GCC internal prototype to avoid an error.
+   Use char because int might match the return type of a GCC
+   builtin and then its argument prototype would still apply.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+char dlopen ();
+int
+main ()
+{
+return dlopen ();
+  ;
+  return 0;
+}
+_ACEOF
+for ac_lib in '' dl dld; do
+  if test -z "$ac_lib"; then
+    ac_res="none required"
+  else
+    ac_res=-l$ac_lib
+    LIBS="-l$ac_lib  $ac_func_search_save_LIBS"
+  fi
+  if ac_fn_cxx_try_link "$LINENO"; then :
+  ac_cv_search_dlopen=$ac_res
+fi
+rm -f core conftest.err conftest.$ac_objext \
+    conftest$ac_exeext
+  if ${ac_cv_search_dlopen+:} false; then :
+  break
+fi
+done
+if ${ac_cv_search_dlopen+:} false; then :
+
+else
+  ac_cv_search_dlopen=no
+fi
+rm conftest.$ac_ext
+LIBS=$ac_func_search_save_LIBS
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_dlopen" >&5
+$as_echo "$ac_cv_search_dlopen" >&6; }
+ac_res=$ac_cv_search_dlopen
+if test "$ac_res" != no; then :
+  test "$ac_res" = "none required" || LIBS="$ac_res $LIBS"
+
+else
+
+  as_fn_error $? "unable to find the dlopen() function" "$LINENO" 5
+
+fi
+
+
 
 # Check whether --with-fesvr was given.
 if test "${with_fesvr+set}" = set; then :
@@ -4086,45 +4141,6 @@ else
 fi
 
 
-# Check whether --enable-fpu was given.
-if test "${enable_fpu+set}" = set; then :
-  enableval=$enable_fpu;
-fi
-
-if test "x$enable_fpu" != "xno"; then :
-
-
-$as_echo "#define RISCV_ENABLE_FPU /**/" >>confdefs.h
-
-
-fi
-
-# Check whether --enable-rvc was given.
-if test "${enable_rvc+set}" = set; then :
-  enableval=$enable_rvc;
-fi
-
-if test "x$enable_rvc" != "xno"; then :
-
-
-$as_echo "#define RISCV_ENABLE_RVC /**/" >>confdefs.h
-
-
-fi
-
-# Check whether --enable-64bit was given.
-if test "${enable_64bit+set}" = set; then :
-  enableval=$enable_64bit;
-fi
-
-if test "x$enable_64bit" != "xno"; then :
-
-
-$as_echo "#define RISCV_ENABLE_64BIT /**/" >>confdefs.h
-
-
-fi
-
 # Check whether --enable-commitlog was given.
 if test "${enable_commitlog+set}" = set; then :
   enableval=$enable_commitlog;
@@ -4330,66 +4346,6 @@ $as_echo "$as_me: configuring default subproject : spike_main" >&6;}
 
 $as_echo "#define SPIKE_MAIN_ENABLED /**/" >>confdefs.h
 
-      { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing dlopen" >&5
-$as_echo_n "checking for library containing dlopen... " >&6; }
-if ${ac_cv_search_dlopen+:} false; then :
-  $as_echo_n "(cached) " >&6
-else
-  ac_func_search_save_LIBS=$LIBS
-cat confdefs.h - <<_ACEOF >conftest.$ac_ext
-/* end confdefs.h.  */
-
-/* Override any GCC internal prototype to avoid an error.
-   Use char because int might match the return type of a GCC
-   builtin and then its argument prototype would still apply.  */
-#ifdef __cplusplus
-extern "C"
-#endif
-char dlopen ();
-int
-main ()
-{
-return dlopen ();
-  ;
-  return 0;
-}
-_ACEOF
-for ac_lib in '' dl dld; do
-  if test -z "$ac_lib"; then
-    ac_res="none required"
-  else
-    ac_res=-l$ac_lib
-    LIBS="-l$ac_lib  $ac_func_search_save_LIBS"
-  fi
-  if ac_fn_cxx_try_link "$LINENO"; then :
-  ac_cv_search_dlopen=$ac_res
-fi
-rm -f core conftest.err conftest.$ac_objext \
-    conftest$ac_exeext
-  if ${ac_cv_search_dlopen+:} false; then :
-  break
-fi
-done
-if ${ac_cv_search_dlopen+:} false; then :
-
-else
-  ac_cv_search_dlopen=no
-fi
-rm conftest.$ac_ext
-LIBS=$ac_func_search_save_LIBS
-fi
-{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_dlopen" >&5
-$as_echo "$ac_cv_search_dlopen" >&6; }
-ac_res=$ac_cv_search_dlopen
-if test "$ac_res" != no; then :
-  test "$ac_res" = "none required" || LIBS="$ac_res $LIBS"
-
-else
-
-  as_fn_error $? "unable to find the dlopen() function" "$LINENO" 5
-
-fi
-
 
 
 

diff --git a/riscv/decode.h b/riscv/decode.h
index 55f03ffcdfb6d7260cf35d11603b2042a952f19d..4d4c447e893304143168374cd951892d9b7d23df 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -45,14 +45,6 @@ const int NFPR = 32;
 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
 
-#ifdef RISCV_ENABLE_RVC
-# define INSN_ALIGNMENT 2
-# define require_rvc
-#else
-# define INSN_ALIGNMENT 4
-# define require_rvc throw trap_illegal_instruction()
-#endif
-
 #define insn_length(x) \
   (((x) & 0x03) < 0x03 ? 2 : \
    ((x) & 0x1f) < 0x1f ? 4 : \
@@ -173,11 +165,8 @@ private:
 #define require_privilege(p) if (get_field(STATE.mstatus, MSTATUS_PRV) < (p)) throw trap_illegal_instruction()
 #define require_rv64 if(unlikely(xlen != 64)) throw trap_illegal_instruction()
 #define require_rv32 if(unlikely(xlen != 32)) throw trap_illegal_instruction()
-#ifdef RISCV_ENABLE_FPU
-# define require_fp if (unlikely((STATE.mstatus & MSTATUS_FS) == 0)) throw trap_illegal_instruction()
-#else
-# define require_fp throw trap_illegal_instruction()
-#endif
+#define require_extension(s) if (!p->supports_extension(s)) throw trap_illegal_instruction()
+#define require_fp if (unlikely((STATE.mstatus & MSTATUS_FS) == 0)) throw trap_illegal_instruction()
 #define require_accelerator if (unlikely((STATE.mstatus & MSTATUS_XS) == 0)) throw trap_illegal_instruction()
 
 #define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \
@@ -189,7 +178,7 @@ private:
 #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
 
 #define set_pc(x) \
-  do { if ((x) & (INSN_ALIGNMENT-1)) \
+  do { if (unlikely(((x) & 2)) && !p->supports_extension('C')) \
          throw trap_instruction_address_misaligned(x); \
        npc = sext_xlen(x); \
      } while(0)

diff --git a/riscv/encoding.h b/riscv/encoding.h
index 0c83ca28fbb734c5aab7719b760f93c898cd1e08..8891ab36b54333684e0d488c6d9164c86dedd07d 100644 (file)
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -48,7 +48,8 @@
 #define VM_MBB   1
 #define VM_MBBID 2
 #define VM_SV32  4
-#define VM_SV43  5
+#define VM_SV39  5
+#define VM_SV48  6
 
 #define UA_RV32  0
 #define UA_RV64  4
@@ -69,7 +70,8 @@
 #define PTE_R      0x040 // Referenced
 #define PTE_D      0x080 // Dirty
 #define PTE_SOFT   0x300 // Reserved for Software
-#define PTE_PPN_SHIFT 10
+#define RV64_PTE_PPN_SHIFT 26
+#define RV32_PTE_PPN_SHIFT 10
 #define PTE_TYPE_INVALID 0
 #define PTE_TYPE_TABLE   1
 #define PTE_TYPE_U       2
@@ -105,13 +107,13 @@
 # define MSTATUS_HA MSTATUS64_HA
 # define MSTATUS_SD MSTATUS64_SD
 # define SSTATUS_SD SSTATUS64_SD
-# define RISCV_PGLEVELS 3 /* Sv39 */
 # define RISCV_PGLEVEL_BITS 9
+# define PTE_PPN_SHIFT RV64_PTE_PPN_SHIFT
 #else
 # define MSTATUS_SD MSTATUS32_SD
 # define SSTATUS_SD SSTATUS32_SD
-# define RISCV_PGLEVELS 2 /* Sv32 */
 # define RISCV_PGLEVEL_BITS 10
+# define PTE_PPN_SHIFT RV32_PTE_PPN_SHIFT
 #endif
 #define RISCV_PGSHIFT 12
 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)

diff --git a/riscv/extensions.cc b/riscv/extensions.cc
new file mode 100644 (file)
index 0000000..315621f
--- /dev/null
+++ b/riscv/extensions.cc
@@ -0,0 +1,35 @@
+#include "extension.h"
+#include <string>
+#include <map>
+#include <dlfcn.h>
+
+static std::map<std::string, std::function<extension_t*()>>& extensions()
+{
+  static std::map<std::string, std::function<extension_t*()>> v;
+  return v;
+}
+
+void register_extension(const char* name, std::function<extension_t*()> f)
+{
+  extensions()[name] = f;
+}
+
+std::function<extension_t*()> find_extension(const char* name)
+{
+  if (!extensions().count(name)) {
+    // try to find extension xyz by loading libxyz.so
+    std::string libname = std::string("lib") + name + ".so";
+    if (!dlopen(libname.c_str(), RTLD_LAZY)) {
+      fprintf(stderr, "couldn't find extension '%s' (or library '%s')\n",
+              name, libname.c_str());
+      exit(-1);
+    }
+    if (!extensions().count(name)) {
+      fprintf(stderr, "couldn't find extension '%s' in shared library '%s'\n",
+              name, libname.c_str());
+      exit(-1);
+    }
+  }
+
+  return extensions()[name];
+}

diff --git a/riscv/insns/amoadd_d.h b/riscv/insns/amoadd_d.h
index c6bacaf57823908d3e13c0715ff78f6105a8e4a2..9c7c124d7c37cbbc5e09ee945c5f3af8d64a2f53 100644 (file)
--- a/riscv/insns/amoadd_d.h
+++ b/riscv/insns/amoadd_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 + v);

diff --git a/riscv/insns/amoadd_w.h b/riscv/insns/amoadd_w.h
index 8eb9e2b020186d78a375a70c0c85fed2a68d769e..7ac59b02442544e96ea1c761011d020037d2b732 100644 (file)
--- a/riscv/insns/amoadd_w.h
+++ b/riscv/insns/amoadd_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 + v);
 WRITE_RD(v);

diff --git a/riscv/insns/amoand_d.h b/riscv/insns/amoand_d.h
index d896ec1fc0056396c751333d57626f31670aa109..7aa6386887002fab5e9cb32aadd38e13179f605b 100644 (file)
--- a/riscv/insns/amoand_d.h
+++ b/riscv/insns/amoand_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 & v);

diff --git a/riscv/insns/amoand_w.h b/riscv/insns/amoand_w.h
index 32ea7f70fa9a643c598e663898b655c8269011cd..7db2160a4538a11b425c33441ea1a43254ecdd81 100644 (file)
--- a/riscv/insns/amoand_w.h
+++ b/riscv/insns/amoand_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 & v);
 WRITE_RD(v);

diff --git a/riscv/insns/amomax_d.h b/riscv/insns/amomax_d.h
index 0a66214a4eade578c7c01f3dedcb568a76c2bc34..0f6da187bc347dacc5972b78e7a52011e4934a99 100644 (file)
--- a/riscv/insns/amomax_d.h
+++ b/riscv/insns/amomax_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 sreg_t v = MMU.load_int64(RS1);
 MMU.store_uint64(RS1, std::max(sreg_t(RS2),v));

diff --git a/riscv/insns/amomax_w.h b/riscv/insns/amomax_w.h
index a2551161bce4e60c6f3df915e3eb06e1cf1c8b42..8c9222bc1b71af3d32eab643496187e395677380 100644 (file)
--- a/riscv/insns/amomax_w.h
+++ b/riscv/insns/amomax_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 int32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::max(int32_t(RS2),v));
 WRITE_RD(v);

diff --git a/riscv/insns/amomaxu_d.h b/riscv/insns/amomaxu_d.h
index dbdb1d2f62a583191efd5b384852c8df2dd26473..6760f9191072acc1bebfa1419ebc2646b315106d 100644 (file)
--- a/riscv/insns/amomaxu_d.h
+++ b/riscv/insns/amomaxu_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, std::max(RS2,v));

diff --git a/riscv/insns/amomaxu_w.h b/riscv/insns/amomaxu_w.h
index 448814bb3b8f084bf12cbde8a1147ddfacda9a58..fc83dc32858ad0923cb6b4f036d386321270b098 100644 (file)
--- a/riscv/insns/amomaxu_w.h
+++ b/riscv/insns/amomaxu_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 uint32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::max(uint32_t(RS2),v));
 WRITE_RD((int32_t)v);

diff --git a/riscv/insns/amomin_d.h b/riscv/insns/amomin_d.h
index 2ad8eef69e017d78c7a9cb4ae7ae4a6f26085275..8d0898461e9aa456498ad02615d1f655142851c4 100644 (file)
--- a/riscv/insns/amomin_d.h
+++ b/riscv/insns/amomin_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 sreg_t v = MMU.load_int64(RS1);
 MMU.store_uint64(RS1, std::min(sreg_t(RS2),v));

diff --git a/riscv/insns/amomin_w.h b/riscv/insns/amomin_w.h
index 28efa15e42f9bdea91a744fba8b85c96322b623d..31a8df86dff8b11ce6c9f91c7a8873f1dcf93445 100644 (file)
--- a/riscv/insns/amomin_w.h
+++ b/riscv/insns/amomin_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 int32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::min(int32_t(RS2),v));
 WRITE_RD(v);

diff --git a/riscv/insns/amominu_d.h b/riscv/insns/amominu_d.h
index 88fe72461c019d1c5fc85d04adc9acaeac167a25..8a77edcfcde14805153aa54e217890504d5d9e27 100644 (file)
--- a/riscv/insns/amominu_d.h
+++ b/riscv/insns/amominu_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, std::min(RS2,v));

diff --git a/riscv/insns/amominu_w.h b/riscv/insns/amominu_w.h
index 459b20161ccb5f47c915a7bad5f669b37751b7f7..2b6aaa3bfc8f24d60a4778924ad0fa385b4e46a7 100644 (file)
--- a/riscv/insns/amominu_w.h
+++ b/riscv/insns/amominu_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 uint32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::min(uint32_t(RS2),v));
 WRITE_RD((int32_t)v);

diff --git a/riscv/insns/amoor_d.h b/riscv/insns/amoor_d.h
index 58a64e082531a89bab89359a232d51af46904c42..5a697172408995031dccafcb8065bf0be1b2306a 100644 (file)
--- a/riscv/insns/amoor_d.h
+++ b/riscv/insns/amoor_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 | v);

diff --git a/riscv/insns/amoor_w.h b/riscv/insns/amoor_w.h
index c178f9af1cc8e8f61bd4a638efbb2118dc9d7227..f5b96b96b2833981db0a0a8dfbe169f96f6a01ac 100644 (file)
--- a/riscv/insns/amoor_w.h
+++ b/riscv/insns/amoor_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 | v);
 WRITE_RD(v);

diff --git a/riscv/insns/amoswap_d.h b/riscv/insns/amoswap_d.h
index 9f34eaa51e4245d54512caf04b115b2d35e0c329..8cf1411fe791b7e382c1f9ac173a4e85d9366f9b 100644 (file)
--- a/riscv/insns/amoswap_d.h
+++ b/riscv/insns/amoswap_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2);

diff --git a/riscv/insns/amoswap_w.h b/riscv/insns/amoswap_w.h
index 148b5bcac1b0924d125f6ba93771ea788f3604eb..0764d59e598c423391a1c188056eeb0cef4477eb 100644 (file)
--- a/riscv/insns/amoswap_w.h
+++ b/riscv/insns/amoswap_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2);
 WRITE_RD(v);

diff --git a/riscv/insns/amoxor_d.h b/riscv/insns/amoxor_d.h
index acd8b6140373839534a91a2a30e1f39e5d0ff7dc..39708223e8bb1a1c790ca97a950f628cb218839f 100644 (file)
--- a/riscv/insns/amoxor_d.h
+++ b/riscv/insns/amoxor_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 ^ v);

diff --git a/riscv/insns/amoxor_w.h b/riscv/insns/amoxor_w.h
index 3a87b6e4550f559455b90a5d0985461466cbb84f..9889b646e3e194540724579e1b3946514e55d115 100644 (file)
--- a/riscv/insns/amoxor_w.h
+++ b/riscv/insns/amoxor_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 ^ v);
 WRITE_RD(v);

diff --git a/riscv/insns/c_add.h b/riscv/insns/c_add.h
index b2ba34f6b52a43b1707a764d74699eb689e24971..c349fc022976fedea123efd6275be767a0e7c966 100644 (file)
--- a/riscv/insns/c_add.h
+++ b/riscv/insns/c_add.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(sext_xlen(RVC_RS1 + RVC_RS2));

diff --git a/riscv/insns/c_addi.h b/riscv/insns/c_addi.h
index 762f5c2fe144b70b3b4a68a2d134e3b6d27586b0..ad278f14d310bd2a9c0ea186c8a8ac923d86643c 100644 (file)
--- a/riscv/insns/c_addi.h
+++ b/riscv/insns/c_addi.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(sext_xlen(RVC_RS2 + insn.rvc_imm()));

diff --git a/riscv/insns/c_addi4.h b/riscv/insns/c_addi4.h
index 90f3d814b40b23f3d8fce9765f634859dbec9f16..3c9b7b22982546c123b57ea47933d37f272d3041 100644 (file)
--- a/riscv/insns/c_addi4.h
+++ b/riscv/insns/c_addi4.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(sext_xlen(RVC_RS2 + insn.rvc_lwsp_imm()));

diff --git a/riscv/insns/c_addiw.h b/riscv/insns/c_addiw.h
index 33f970c271fcbbf03fa9aaac689794ab319b2ba9..1b81834ebcf22fb0becff2dbd3434780575bb725 100644 (file)
--- a/riscv/insns/c_addiw.h
+++ b/riscv/insns/c_addiw.h
@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
 WRITE_RD(sext32(RVC_RS2 + insn.rvc_imm()));

diff --git a/riscv/insns/c_addw.h b/riscv/insns/c_addw.h
index c474cda73a6afeb4581a6ab21c3a1682f1d61804..fef554d1f62ed7cce7e27b7ad5c2f220e667c98c 100644 (file)
--- a/riscv/insns/c_addw.h
+++ b/riscv/insns/c_addw.h
@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
 WRITE_RD(sext32(RVC_RS1 + RVC_RS2));

diff --git a/riscv/insns/c_beqz.h b/riscv/insns/c_beqz.h
index 8fee5bc2f11dd148972eff6765f42620cdc0f9fd..35c119603d08ab51bc87d391a324e24a7d0cf972 100644 (file)
--- a/riscv/insns/c_beqz.h
+++ b/riscv/insns/c_beqz.h
@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 if (RVC_RS1S == 0)
   set_pc(pc + insn.rvc_b_imm());

diff --git a/riscv/insns/c_bnez.h b/riscv/insns/c_bnez.h
index a1a56665e46811286aef9023fad8dc9b07d3cefd..1e40ea78e19fc05b6edc74baf09ed2e8f525c321 100644 (file)
--- a/riscv/insns/c_bnez.h
+++ b/riscv/insns/c_bnez.h
@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 if (RVC_RS1S != 0)
   set_pc(pc + insn.rvc_b_imm());

diff --git a/riscv/insns/c_j.h b/riscv/insns/c_j.h
index f57022ddb45a6ce287a9cc52de31ebc82c510d23..6d8939c47fc40b4e06f7126c22f48e5137ad4175 100644 (file)
--- a/riscv/insns/c_j.h
+++ b/riscv/insns/c_j.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 set_pc(pc + insn.rvc_j_imm());

diff --git a/riscv/insns/c_jalr.h b/riscv/insns/c_jalr.h
index 9fd7f5d0f444e6f9c40428947d041f24fa83170a..ef6edfc966ad809db6e559d5902313d0a8f0e982 100644 (file)
--- a/riscv/insns/c_jalr.h
+++ b/riscv/insns/c_jalr.h
@@ -1,4 +1,4 @@
-require_rvc;
+require_extension('C');
 reg_t tmp = npc;
 set_pc(RVC_RS1 & ~reg_t(1));
 WRITE_RD(tmp);

diff --git a/riscv/insns/c_ld.h b/riscv/insns/c_ld.h
index 37b0ee2c630dd3f1e672f70f34427b4349f1d28b..df0f5c31338c2445c7539f1c88f0708b28279e99 100644 (file)
--- a/riscv/insns/c_ld.h
+++ b/riscv/insns/c_ld.h
@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
 WRITE_RVC_RDS(MMU.load_int64(RVC_RS1S + insn.rvc_ld_imm()));

diff --git a/riscv/insns/c_ldsp.h b/riscv/insns/c_ldsp.h
index 0b8bcbe9a7f74df36a913f38619b49c331c65e4c..42665cfed0e0f40629fcd56846a4b64e06425312 100644 (file)
--- a/riscv/insns/c_ldsp.h
+++ b/riscv/insns/c_ldsp.h
@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
 WRITE_RD(MMU.load_int64(RVC_SP + insn.rvc_ldsp_imm()));

diff --git a/riscv/insns/c_li.h b/riscv/insns/c_li.h
index b53c958676997782e9eb90b86f9e22534b90640a..06d7bf2ae286f96b542a9401cc5d309d105221d5 100644 (file)
--- a/riscv/insns/c_li.h
+++ b/riscv/insns/c_li.h
@@ -1,4 +1,4 @@
-require_rvc;
+require_extension('C');
 if (insn.rvc_rd() == 0) {
   if (insn.rvc_imm() == -32) // c.sbreak
     throw trap_breakpoint();

diff --git a/riscv/insns/c_lui.h b/riscv/insns/c_lui.h
index abdb78ee2bb6e5fc178c6ab2315832eec9dfd25a..4bd4f87de91f034268cec9870dae326f48273e0a 100644 (file)
--- a/riscv/insns/c_lui.h
+++ b/riscv/insns/c_lui.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(insn.rvc_imm() << 12);

diff --git a/riscv/insns/c_lw.h b/riscv/insns/c_lw.h
index 9c6f470cd23ec1137ba78cfb826e27b65dff870e..f2fc2991d32a0fe5925cf048c8a6bf9fb0892605 100644 (file)
--- a/riscv/insns/c_lw.h
+++ b/riscv/insns/c_lw.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RVC_RDS(MMU.load_int32(RVC_RS1S + insn.rvc_lw_imm()));

diff --git a/riscv/insns/c_lwsp.h b/riscv/insns/c_lwsp.h
index 8d9b9e3bf845326187998905ab39c11db1597bb3..ed4dcf30887e4e299fd2cff5835a4faf521dc3e5 100644 (file)
--- a/riscv/insns/c_lwsp.h
+++ b/riscv/insns/c_lwsp.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm()));

diff --git a/riscv/insns/c_mv.h b/riscv/insns/c_mv.h
index 6de658465c455113c2d2551ad92f602ce3ec5362..bc05cfe9d72e86a5bef14ef943171e319ab9c490 100644 (file)
--- a/riscv/insns/c_mv.h
+++ b/riscv/insns/c_mv.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(RVC_RS1);

diff --git a/riscv/insns/c_sd.h b/riscv/insns/c_sd.h
index 13de934cf99fc40e899268a613b69801f20b3f90..9262d044792c94947d234af5d1d73136fe25ac98 100644 (file)
--- a/riscv/insns/c_sd.h
+++ b/riscv/insns/c_sd.h
@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
 MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);

diff --git a/riscv/insns/c_sdsp.h b/riscv/insns/c_sdsp.h
index 6028b0fbf73f8904016081697268b0ce5e6882d4..e8b51706b5203f331f5901ca61151c6048942617 100644 (file)
--- a/riscv/insns/c_sdsp.h
+++ b/riscv/insns/c_sdsp.h
@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
 MMU.store_uint64(RVC_SP + insn.rvc_ldsp_imm(), RVC_RS2);

diff --git a/riscv/insns/c_slli.h b/riscv/insns/c_slli.h
index fb6dffd3a331a2f88dec85b23415eccc42b10093..de3683b9e4a547d77b11f0ce270dffa87c01dca5 100644 (file)
--- a/riscv/insns/c_slli.h
+++ b/riscv/insns/c_slli.h
@@ -1,4 +1,4 @@
-require_rvc;
+require_extension('C');
 if (insn.rvc_imm() >= xlen)
   throw trap_illegal_instruction();
 WRITE_RD(sext_xlen(RVC_RS2 << insn.rvc_imm()));

diff --git a/riscv/insns/c_sw.h b/riscv/insns/c_sw.h
index 34deb9dc0c309ecef06814b8aeee884f12ae45e1..3073e9d623dcb98265b2c1d1d3c59f51530ab386 100644 (file)
--- a/riscv/insns/c_sw.h
+++ b/riscv/insns/c_sw.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_RS2S);

diff --git a/riscv/insns/c_swsp.h b/riscv/insns/c_swsp.h
index bbb5ad058b598f43691637772dab4a4c9b479e63..6f3fef0dcdf15855f30a3a3e4a35ee5c6d4e7182 100644 (file)
--- a/riscv/insns/c_swsp.h
+++ b/riscv/insns/c_swsp.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 MMU.store_uint32(RVC_SP + insn.rvc_lwsp_imm(), RVC_RS2);

diff --git a/riscv/insns/div.h b/riscv/insns/div.h
index 3ad613a1113ff3c156720b7028aedea9a937e729..9cbe8d6b321648b144834ef2514948c1b8f19bff 100644 (file)
--- a/riscv/insns/div.h
+++ b/riscv/insns/div.h
@@ -1,3 +1,4 @@
+require_extension('M');
 sreg_t lhs = sext_xlen(RS1);
 sreg_t rhs = sext_xlen(RS2);
 if(rhs == 0)

diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h
index 4887ce0a6037cbc78e2b3833d57e21de21f34482..31d758560b8e5b9074c74292b871f32bd5207d06 100644 (file)
--- a/riscv/insns/divu.h
+++ b/riscv/insns/divu.h
@@ -1,3 +1,4 @@
+require_extension('M');
 reg_t lhs = zext_xlen(RS1);
 reg_t rhs = zext_xlen(RS2);
 if(rhs == 0)

diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
index a613d958fe190caded039fd6326cf468234e7834..e127619aa990ad3394c16810268be611543ef221 100644 (file)
--- a/riscv/insns/divuw.h
+++ b/riscv/insns/divuw.h
@@ -1,3 +1,4 @@
+require_extension('M');
 require_rv64;
 reg_t lhs = zext32(RS1);
 reg_t rhs = zext32(RS2);

diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index bd4e999f65dad1aa72dd91aa96b99e310991aed1..11be17e4c33d450244c42d98c99d2c31c8a35bd9 100644 (file)
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -1,3 +1,4 @@
+require_extension('M');
 require_rv64;
 sreg_t lhs = sext32(RS1);
 sreg_t rhs = sext32(RS2);

diff --git a/riscv/insns/fadd_d.h b/riscv/insns/fadd_d.h
index e06efb85b868a19c04d75f96f9623c08d0a5e897..3e5963dc99b86c4f5ec1eb90a9a1803a434b908c 100644 (file)
--- a/riscv/insns/fadd_d.h
+++ b/riscv/insns/fadd_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2));

diff --git a/riscv/insns/fadd_h.h b/riscv/insns/fadd_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fadd_s.h b/riscv/insns/fadd_s.h
index c43135dec2459771da04798050886f8c81abb735..a35a5248872436e97b4667a811172c5627b62731 100644 (file)
--- a/riscv/insns/fadd_s.h
+++ b/riscv/insns/fadd_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_mulAdd(FRS1, 0x3f800000, FRS2));

diff --git a/riscv/insns/fclass_d.h b/riscv/insns/fclass_d.h
index bd42d45a3b1e0dc92bb2fe0fa8b953f97690037b..f4883ef27f44f416b8000520f625c07c62293235 100644 (file)
--- a/riscv/insns/fclass_d.h
+++ b/riscv/insns/fclass_d.h
@@ -1,2 +1,3 @@
+require_extension('D');
 require_fp;
 WRITE_RD(f64_classify(FRS1));

diff --git a/riscv/insns/fclass_s.h b/riscv/insns/fclass_s.h
index a01026603b88ca98ac07bc21ec5daef0a8de7d47..a2d5b63be69479c9f111dab6d8ef00a709b7d990 100644 (file)
--- a/riscv/insns/fclass_s.h
+++ b/riscv/insns/fclass_s.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 WRITE_RD(f32_classify(FRS1));

diff --git a/riscv/insns/fcvt_d_h.h b/riscv/insns/fcvt_d_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fcvt_d_l.h b/riscv/insns/fcvt_d_l.h
index e0e18245f3b62c2f30c09305d803d427c4e9fdc5..08716cffe2d6af6f3f6844381c84b56c40e8d4fe 100644 (file)
--- a/riscv/insns/fcvt_d_l.h
+++ b/riscv/insns/fcvt_d_l.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;

diff --git a/riscv/insns/fcvt_d_lu.h b/riscv/insns/fcvt_d_lu.h
index ee338480d72bec372e1b070d19a527591b6959c4..306d7fedd8c9889f6255ab12c5da2867ac734daa 100644 (file)
--- a/riscv/insns/fcvt_d_lu.h
+++ b/riscv/insns/fcvt_d_lu.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;

diff --git a/riscv/insns/fcvt_d_s.h b/riscv/insns/fcvt_d_s.h
index 0024330730e45a108db4fcd044c54a27e7ad86d1..177e77cac0cc20d244c9dd80a4f30706d6a3cf37 100644 (file)
--- a/riscv/insns/fcvt_d_s.h
+++ b/riscv/insns/fcvt_d_s.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_to_f64(FRS1));

diff --git a/riscv/insns/fcvt_d_w.h b/riscv/insns/fcvt_d_w.h
index ce56974aa7c0e1b6249c86d65c9a8631ef959345..4c4861c1555c48c9e136086de2890a568e9ddb2e 100644 (file)
--- a/riscv/insns/fcvt_d_w.h
+++ b/riscv/insns/fcvt_d_w.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(i32_to_f64((int32_t)RS1));

diff --git a/riscv/insns/fcvt_d_wu.h b/riscv/insns/fcvt_d_wu.h
index 4c562481e200f869f06e6c5aeaf4848331f7ed0b..1dbf218a1cfa95a4799bb9606e0d35d3f89c9e7f 100644 (file)
--- a/riscv/insns/fcvt_d_wu.h
+++ b/riscv/insns/fcvt_d_wu.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(ui32_to_f64((uint32_t)RS1));

diff --git a/riscv/insns/fcvt_h_d.h b/riscv/insns/fcvt_h_d.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fcvt_h_l.h b/riscv/insns/fcvt_h_l.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fcvt_h_lu.h b/riscv/insns/fcvt_h_lu.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fcvt_h_s.h b/riscv/insns/fcvt_h_s.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fcvt_h_w.h b/riscv/insns/fcvt_h_w.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fcvt_h_wu.h b/riscv/insns/fcvt_h_wu.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fcvt_l_d.h b/riscv/insns/fcvt_l_d.h
index 55dbe27d2b70e491585012098607e0a0d20cc82e..ee323f34be8bb46b1a7da944faea112947bfad9a 100644 (file)
--- a/riscv/insns/fcvt_l_d.h
+++ b/riscv/insns/fcvt_l_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;

diff --git a/riscv/insns/fcvt_l_h.h b/riscv/insns/fcvt_l_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fcvt_l_s.h b/riscv/insns/fcvt_l_s.h
index ea1e5a7084fdb2b0ba7618496f8979cc5feb0564..6079a6976cfbab5e0f2cf20ae40d9c1d15623de2 100644 (file)
--- a/riscv/insns/fcvt_l_s.h
+++ b/riscv/insns/fcvt_l_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;

diff --git a/riscv/insns/fcvt_lu_d.h b/riscv/insns/fcvt_lu_d.h
index 7be12ed266f207f86e8fe446ba4819d3e8c5a204..b6004eaf00e51591caf6fdd4c9b61b05f23230e0 100644 (file)
--- a/riscv/insns/fcvt_lu_d.h
+++ b/riscv/insns/fcvt_lu_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;

diff --git a/riscv/insns/fcvt_lu_h.h b/riscv/insns/fcvt_lu_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fcvt_lu_s.h b/riscv/insns/fcvt_lu_s.h
index 04501c196eff7999762af9ac1410644f1d3d55a4..af8e1aba561fc4f1d7368eb39547d6b0535eae9e 100644 (file)
--- a/riscv/insns/fcvt_lu_s.h
+++ b/riscv/insns/fcvt_lu_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;

diff --git a/riscv/insns/fcvt_s_d.h b/riscv/insns/fcvt_s_d.h
index 28a1d6969df2092d300991f5e5bb6d6f42308ce8..c1c9f0cf887e10ef963c7b233ae04969be0aa3de 100644 (file)
--- a/riscv/insns/fcvt_s_d.h
+++ b/riscv/insns/fcvt_s_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_to_f32(FRS1));

diff --git a/riscv/insns/fcvt_s_h.h b/riscv/insns/fcvt_s_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fcvt_s_l.h b/riscv/insns/fcvt_s_l.h
index 723b9e42c5d1e50478457d606c5e966004435745..9abcc80509eaac8d7b256e6edb98180d48659716 100644 (file)
--- a/riscv/insns/fcvt_s_l.h
+++ b/riscv/insns/fcvt_s_l.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;

diff --git a/riscv/insns/fcvt_s_lu.h b/riscv/insns/fcvt_s_lu.h
index b58b395757b79b580097b634b457969f63e9c341..70c676edf410ba60fdc3be0599a03077ea8f6d48 100644 (file)
--- a/riscv/insns/fcvt_s_lu.h
+++ b/riscv/insns/fcvt_s_lu.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;

diff --git a/riscv/insns/fcvt_s_w.h b/riscv/insns/fcvt_s_w.h
index 05445fa27a7bb4aaee125eac7caafe9f7e06390d..1ddabd87c12cda406cc3e924ba9c3103815d8298 100644 (file)
--- a/riscv/insns/fcvt_s_w.h
+++ b/riscv/insns/fcvt_s_w.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(i32_to_f32((int32_t)RS1));

diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h
index ca8d2b603f5fcc60e698cd29cf35b2e923a005dc..c1394c3fd04af3f078f9cd29d201a52c63e199e4 100644 (file)
--- a/riscv/insns/fcvt_s_wu.h
+++ b/riscv/insns/fcvt_s_wu.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(ui32_to_f32((uint32_t)RS1));

diff --git a/riscv/insns/fcvt_w_d.h b/riscv/insns/fcvt_w_d.h
index a5186b5a57a16e7067565f7e58719e7bffe99966..bac8a9b344aaa53be28aa365dd741045be7f7076 100644 (file)
--- a/riscv/insns/fcvt_w_d.h
+++ b/riscv/insns/fcvt_w_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_RD(sext32(f64_to_i32(FRS1, RM, true)));

diff --git a/riscv/insns/fcvt_w_h.h b/riscv/insns/fcvt_w_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fcvt_w_s.h b/riscv/insns/fcvt_w_s.h
index 1d82deb72727468fcfc150800f58d87a5f67cc7d..81bc89ff8d8ed48323a5c5ab0b26bf28007953ab 100644 (file)
--- a/riscv/insns/fcvt_w_s.h
+++ b/riscv/insns/fcvt_w_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_RD(sext32(f32_to_i32(FRS1, RM, true)));

diff --git a/riscv/insns/fcvt_wu_d.h b/riscv/insns/fcvt_wu_d.h
index 5cf44d153721eb525241c9253b4a616d5e897ff0..353ae6d88d8120344d339804dba63ccc3d54419d 100644 (file)
--- a/riscv/insns/fcvt_wu_d.h
+++ b/riscv/insns/fcvt_wu_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_RD(sext32(f64_to_ui32(FRS1, RM, true)));

diff --git a/riscv/insns/fcvt_wu_h.h b/riscv/insns/fcvt_wu_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fcvt_wu_s.h b/riscv/insns/fcvt_wu_s.h
index 5b4c4444bab2d0cceb8eebdbde5e1f8eb9124ec1..2c1ff005ec660a97f6ca11f629ae0d38f8ea947d 100644 (file)
--- a/riscv/insns/fcvt_wu_s.h
+++ b/riscv/insns/fcvt_wu_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_RD(sext32(f32_to_ui32(FRS1, RM, true)));

diff --git a/riscv/insns/fdiv_d.h b/riscv/insns/fdiv_d.h
index e21570278522f29d4cdc21afd403c3e2baea8377..d52ac667b5e05ec4edd80400d50da0f7dc609c8e 100644 (file)
--- a/riscv/insns/fdiv_d.h
+++ b/riscv/insns/fdiv_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_div(FRS1, FRS2));

diff --git a/riscv/insns/fdiv_h.h b/riscv/insns/fdiv_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fdiv_s.h b/riscv/insns/fdiv_s.h
index 2644d08828d2c2be8570df6aabbf9ea18d1a57ca..cf54c575c1d87e25fa88bccba608adf7932dd45f 100644 (file)
--- a/riscv/insns/fdiv_s.h
+++ b/riscv/insns/fdiv_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_div(FRS1, FRS2));

diff --git a/riscv/insns/feq_d.h b/riscv/insns/feq_d.h
index 516fb5965cb1dac9525b17428fe73770c1015581..43d9c1cda01673b3a3a0d7d0448a97ef759738b7 100644 (file)
--- a/riscv/insns/feq_d.h
+++ b/riscv/insns/feq_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 WRITE_RD(f64_eq(FRS1, FRS2));
 set_fp_exceptions;

diff --git a/riscv/insns/feq_h.h b/riscv/insns/feq_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/feq_s.h b/riscv/insns/feq_s.h
index b44da24e02b794536ff9535652427d7e97beb49b..7d426345aaf04b65ce18faf106122f00f350bc6c 100644 (file)
--- a/riscv/insns/feq_s.h
+++ b/riscv/insns/feq_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 WRITE_RD(f32_eq(FRS1, FRS2));
 set_fp_exceptions;

diff --git a/riscv/insns/fld.h b/riscv/insns/fld.h
index 1bc83cfdeef0d5c50c220591021ef1dbb93c0072..0b50b8a5ac147dd0112f0bb9ca05c5300a532f03 100644 (file)
--- a/riscv/insns/fld.h
+++ b/riscv/insns/fld.h
@@ -1,2 +1,3 @@
+require_extension('D');
 require_fp;
 WRITE_FRD(MMU.load_int64(RS1 + insn.i_imm()));

diff --git a/riscv/insns/fle_d.h b/riscv/insns/fle_d.h
index 72dcc7e650560d450c357cb43b83e6d373ab64d5..7f6a84d6b4079cb1498365badddaeaf2f5998dcb 100644 (file)
--- a/riscv/insns/fle_d.h
+++ b/riscv/insns/fle_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 WRITE_RD(f64_le(FRS1, FRS2));
 set_fp_exceptions;

diff --git a/riscv/insns/fle_h.h b/riscv/insns/fle_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fle_s.h b/riscv/insns/fle_s.h
index 9c85b4a586b750fc74657dd652555300a7e9c227..0884c5197ce789e25290e620c829f8a12aaea388 100644 (file)
--- a/riscv/insns/fle_s.h
+++ b/riscv/insns/fle_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 WRITE_RD(f32_le(FRS1, FRS2));
 set_fp_exceptions;

diff --git a/riscv/insns/flh.h b/riscv/insns/flh.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/flt_d.h b/riscv/insns/flt_d.h
index 335e4a80125d47d0d1e0ead1097c0c3123cbeb4f..9fda98dd767dcbb7537aacb619dccadb60b2d63d 100644 (file)
--- a/riscv/insns/flt_d.h
+++ b/riscv/insns/flt_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 WRITE_RD(f64_lt(FRS1, FRS2));
 set_fp_exceptions;

diff --git a/riscv/insns/flt_h.h b/riscv/insns/flt_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/flt_s.h b/riscv/insns/flt_s.h
index 7a2178521c0e930a80cc256f6fe21fced6e50750..830b0a08a3a2134a87822ad392ecf0eb1823dda8 100644 (file)
--- a/riscv/insns/flt_s.h
+++ b/riscv/insns/flt_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 WRITE_RD(f32_lt(FRS1, FRS2));
 set_fp_exceptions;

diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h
index a5f7d16eaab263ec39022ea4f342d5cc5affbbb4..b94ba5dd6e8c7958d6a24c3c5df2e93426cba42a 100644 (file)
--- a/riscv/insns/flw.h
+++ b/riscv/insns/flw.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 WRITE_FRD(MMU.load_int32(RS1 + insn.i_imm()));

diff --git a/riscv/insns/fmadd_d.h b/riscv/insns/fmadd_d.h
index 8640e7f46e17fa4b2447c45803c42f49d87560e7..8605e0be8811e7be10a118103e02785c1d324cb8 100644 (file)
--- a/riscv/insns/fmadd_d.h
+++ b/riscv/insns/fmadd_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_mulAdd(FRS1, FRS2, FRS3));

diff --git a/riscv/insns/fmadd_h.h b/riscv/insns/fmadd_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fmadd_s.h b/riscv/insns/fmadd_s.h
index f8b0a5f1ada3112efb31645ee769f20a5e3ede8c..95196b717f075cfb6837e424c9b9878f465d36cf 100644 (file)
--- a/riscv/insns/fmadd_s.h
+++ b/riscv/insns/fmadd_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_mulAdd(FRS1, FRS2, FRS3));

diff --git a/riscv/insns/fmax_d.h b/riscv/insns/fmax_d.h
index a26aeabb4c6537d9fcf3990df9febcff9aec29be..eb156de9f0a67e00e5e8ddbe2f08e0773417a013 100644 (file)
--- a/riscv/insns/fmax_d.h
+++ b/riscv/insns/fmax_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 WRITE_FRD(isNaNF64UI(FRS2) || f64_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
       ? FRS1 : FRS2);

diff --git a/riscv/insns/fmax_h.h b/riscv/insns/fmax_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fmax_s.h b/riscv/insns/fmax_s.h
index b16134bbf8fed3482a7c595fcf524a7db87cf545..215a6d14565410fd347a2350fc7624a156f6470b 100644 (file)
--- a/riscv/insns/fmax_s.h
+++ b/riscv/insns/fmax_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 WRITE_FRD(isNaNF32UI(FRS2) || f32_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
       ? FRS1 : FRS2);

diff --git a/riscv/insns/fmin_d.h b/riscv/insns/fmin_d.h
index c095adee4587f860f26e0a2dce8963a94bf366b5..02ea6810d34f64063f8e9cac94e74af152839807 100644 (file)
--- a/riscv/insns/fmin_d.h
+++ b/riscv/insns/fmin_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 WRITE_FRD(isNaNF64UI(FRS2) || f64_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
       ? FRS1 : FRS2);

diff --git a/riscv/insns/fmin_h.h b/riscv/insns/fmin_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h
index e2fdc5c3bcec4276ca28af21c2a86b679a3116eb..cc673a0cab87f8ad12ff6d0cd05c150475809370 100644 (file)
--- a/riscv/insns/fmin_s.h
+++ b/riscv/insns/fmin_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 WRITE_FRD(isNaNF32UI(FRS2) || f32_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
       ? FRS1 : FRS2);

diff --git a/riscv/insns/fmsub_d.h b/riscv/insns/fmsub_d.h
index 13e9fcc6623f61e43f0fcd5e9aec0bfc4027d89f..696f8226ec90fa77de89c67b8f46586681f6eee9 100644 (file)
--- a/riscv/insns/fmsub_d.h
+++ b/riscv/insns/fmsub_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN));

diff --git a/riscv/insns/fmsub_h.h b/riscv/insns/fmsub_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fmsub_s.h b/riscv/insns/fmsub_s.h
index c6aa418521cdc9952538c5774201f9a733506c37..92512772c6d4c0ada2fe52133024847207b927cd 100644 (file)
--- a/riscv/insns/fmsub_s.h
+++ b/riscv/insns/fmsub_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN));

diff --git a/riscv/insns/fmul_d.h b/riscv/insns/fmul_d.h
index e2ca1c2a68445ee74b9af3adc0c8e8072583d7fb..d74c316b679589609b246e463822c1bb021ab16f 100644 (file)
--- a/riscv/insns/fmul_d.h
+++ b/riscv/insns/fmul_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint64_t)INT64_MIN));

diff --git a/riscv/insns/fmul_h.h b/riscv/insns/fmul_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fmul_s.h b/riscv/insns/fmul_s.h
index f564803475ca4cb6b78f324b140793e288138470..284aeb399edf77863f98784336c31f6c643ab739 100644 (file)
--- a/riscv/insns/fmul_s.h
+++ b/riscv/insns/fmul_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint32_t)INT32_MIN));

diff --git a/riscv/insns/fmv_d_x.h b/riscv/insns/fmv_d_x.h
index f01811d3ab6f70d51f36da4ed6d0b447e7dcf4a0..c3f6049316b1f3be58a6d9305ba9419f913c8f20 100644 (file)
--- a/riscv/insns/fmv_d_x.h
+++ b/riscv/insns/fmv_d_x.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_rv64;
 require_fp;
 WRITE_FRD(RS1);

diff --git a/riscv/insns/fmv_h_x.h b/riscv/insns/fmv_h_x.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fmv_s_x.h b/riscv/insns/fmv_s_x.h
index f3eac828625486d3590c9138761ebfa07b6bd7cd..f0f95aca06b7bea9b73032c7a8c9f6dbe273c08f 100644 (file)
--- a/riscv/insns/fmv_s_x.h
+++ b/riscv/insns/fmv_s_x.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 WRITE_FRD(RS1);

diff --git a/riscv/insns/fmv_x_d.h b/riscv/insns/fmv_x_d.h
index d3c1d7aab83c1a18ce35a59cfa47f5e1eb8f6f95..b97d7f59bacefafcaad9f0e964b96098c8f1c0a2 100644 (file)
--- a/riscv/insns/fmv_x_d.h
+++ b/riscv/insns/fmv_x_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_rv64;
 require_fp;
 WRITE_RD(FRS1);

diff --git a/riscv/insns/fmv_x_h.h b/riscv/insns/fmv_x_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fmv_x_s.h b/riscv/insns/fmv_x_s.h
index 46a94886e6b63fe7658b70ff1aab4aad2e1856a4..1bee87f4aa5fa61cd98bf1a70dde5b51f9bcf169 100644 (file)
--- a/riscv/insns/fmv_x_s.h
+++ b/riscv/insns/fmv_x_s.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 WRITE_RD(sext32(FRS1));

diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h
index 705470bf9294e2f4afe6cfaaa9914d656d86c5d9..bed6172b3419e1cb449826fd94ee2b4c5815a712 100644 (file)
--- a/riscv/insns/fnmadd_d.h
+++ b/riscv/insns/fnmadd_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3 ^ (uint64_t)INT64_MIN));

diff --git a/riscv/insns/fnmadd_h.h b/riscv/insns/fnmadd_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h
index 2df321b5f9eb4088f6d9f5e304f372be45407833..1378ae33375ceb0ff4ef9023e3c56362a9a20054 100644 (file)
--- a/riscv/insns/fnmadd_s.h
+++ b/riscv/insns/fnmadd_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3 ^ (uint32_t)INT32_MIN));

diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h
index c38d2bf0608ebde7311967fce9b0da777b08b9d9..340090aafaa88abcddd763183f38cd64926be54e 100644 (file)
--- a/riscv/insns/fnmsub_d.h
+++ b/riscv/insns/fnmsub_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3));

diff --git a/riscv/insns/fnmsub_h.h b/riscv/insns/fnmsub_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h
index c3fa995869ba3b2d98762f10da123a0d83bde52f..3be27d09b5f01d952855d024a9cf1ca4ae4e06d6 100644 (file)
--- a/riscv/insns/fnmsub_s.h
+++ b/riscv/insns/fnmsub_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3));

diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h
index fe90a6b6320f46707108e80b2c05ca626e6eb235..63cc8e5fc00eae9fefaa954db7a0b09cddce3039 100644 (file)
--- a/riscv/insns/fsd.h
+++ b/riscv/insns/fsd.h
@@ -1,2 +1,3 @@
+require_extension('D');
 require_fp;
 MMU.store_uint64(RS1 + insn.s_imm(), FRS2);

diff --git a/riscv/insns/fsgnj_d.h b/riscv/insns/fsgnj_d.h
index 74ef3f6c652422aaac9dd2661ae3d611d49ded29..52648a1a78649b790df944dc86f15d4d04986642 100644 (file)
--- a/riscv/insns/fsgnj_d.h
+++ b/riscv/insns/fsgnj_d.h
@@ -1,2 +1,3 @@
+require_extension('D');
 require_fp;
 WRITE_FRD((FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN));

diff --git a/riscv/insns/fsgnj_h.h b/riscv/insns/fsgnj_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fsgnj_s.h b/riscv/insns/fsgnj_s.h
index 4f852b43e1b86c7a580aa93f086c3250db906a15..4c91ff327531125047d006ee24a563bc7b02838c 100644 (file)
--- a/riscv/insns/fsgnj_s.h
+++ b/riscv/insns/fsgnj_s.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 WRITE_FRD((FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN));

diff --git a/riscv/insns/fsgnjn_d.h b/riscv/insns/fsgnjn_d.h
index e214f1d7c3649a0b8d6c73b7265734e904c2b08a..cdec924ba8042c4b06ad8ccbffaf0c66bc1542ae 100644 (file)
--- a/riscv/insns/fsgnjn_d.h
+++ b/riscv/insns/fsgnjn_d.h
@@ -1,2 +1,3 @@
+require_extension('D');
 require_fp;
 WRITE_FRD((FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN));

diff --git a/riscv/insns/fsgnjn_h.h b/riscv/insns/fsgnjn_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fsgnjn_s.h b/riscv/insns/fsgnjn_s.h
index b098150c79ba8fd2776911c08e1c3304608b569c..f91a7b0a43c72482d9c8600e5678c8590a5986ad 100644 (file)
--- a/riscv/insns/fsgnjn_s.h
+++ b/riscv/insns/fsgnjn_s.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 WRITE_FRD((FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN));

diff --git a/riscv/insns/fsgnjx_d.h b/riscv/insns/fsgnjx_d.h
index 2bcef6f306a84573a5d4e81ea8e69483da89ad2c..b09d24cb8fe48b9394e2589afc165b2ef717ccf5 100644 (file)
--- a/riscv/insns/fsgnjx_d.h
+++ b/riscv/insns/fsgnjx_d.h
@@ -1,2 +1,3 @@
+require_extension('D');
 require_fp;
 WRITE_FRD(FRS1 ^ (FRS2 & INT64_MIN));

diff --git a/riscv/insns/fsgnjx_h.h b/riscv/insns/fsgnjx_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fsgnjx_s.h b/riscv/insns/fsgnjx_s.h
index 69b2d98c4b0c4c0de47ba7d6377e660b55e55978..1fd2de6b94b3af36241e956077050a5e77b7adc8 100644 (file)
--- a/riscv/insns/fsgnjx_s.h
+++ b/riscv/insns/fsgnjx_s.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 WRITE_FRD(FRS1 ^ (FRS2 & (uint32_t)INT32_MIN));

diff --git a/riscv/insns/fsh.h b/riscv/insns/fsh.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fsqrt_d.h b/riscv/insns/fsqrt_d.h
index 0ff5daa84544f3e04b4bcfa267def13eb9da4de3..812438c308ef2052ef339bb3cc6c580c13e347db 100644 (file)
--- a/riscv/insns/fsqrt_d.h
+++ b/riscv/insns/fsqrt_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_sqrt(FRS1));

diff --git a/riscv/insns/fsqrt_h.h b/riscv/insns/fsqrt_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fsqrt_s.h b/riscv/insns/fsqrt_s.h
index ea1f31ac85bbca49be63e4655e1b3507f944a7b5..d77acab3f0a34ba309ef65513f558b42fb23b6dd 100644 (file)
--- a/riscv/insns/fsqrt_s.h
+++ b/riscv/insns/fsqrt_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_sqrt(FRS1));

diff --git a/riscv/insns/fsub_d.h b/riscv/insns/fsub_d.h
index 238ee9e8fb536148dabb0002820ec75310bcd28d..6ffc6b31ded449283dea80667c424dc7a936ba10 100644 (file)
--- a/riscv/insns/fsub_d.h
+++ b/riscv/insns/fsub_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2 ^ (uint64_t)INT64_MIN));

diff --git a/riscv/insns/fsub_h.h b/riscv/insns/fsub_h.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fsub_s.h b/riscv/insns/fsub_s.h
index a30b4f9b82f250b7eef205b6f320e2b24f51c007..6a0f853f4739f07d337afb07d39afa21de65bc84 100644 (file)
--- a/riscv/insns/fsub_s.h
+++ b/riscv/insns/fsub_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_mulAdd(FRS1, 0x3f800000, FRS2 ^ (uint32_t)INT32_MIN));

diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h
index 85c8091ab16af0a2c8d15f86310dc2b5ee27fb98..3135e9b7dace76cc7866b46d6415965ade82a84f 100644 (file)
--- a/riscv/insns/fsw.h
+++ b/riscv/insns/fsw.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 MMU.store_uint32(RS1 + insn.s_imm(), FRS2);

diff --git a/riscv/insns/lr_d.h b/riscv/insns/lr_d.h
index 94c4bf732bad3d86775bfd8ec3cc1d958c25e6ee..077590f65950bc886b4af3150ba09b9f9a620658 100644 (file)
--- a/riscv/insns/lr_d.h
+++ b/riscv/insns/lr_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 p->get_state()->load_reservation = RS1;
 WRITE_RD(MMU.load_int64(RS1));

diff --git a/riscv/insns/lr_w.h b/riscv/insns/lr_w.h
index 2b954195b79b9eca3ca5289b1b1efaf0db6880c5..767251f9e07775dfe2edc01b726f1f661e43feb5 100644 (file)
--- a/riscv/insns/lr_w.h
+++ b/riscv/insns/lr_w.h
@@ -1,2 +1,3 @@
+require_extension('A');
 p->get_state()->load_reservation = RS1;
 WRITE_RD(MMU.load_int32(RS1));

diff --git a/riscv/insns/mul.h b/riscv/insns/mul.h
index c6b53311e6df7839bc545740a582bbfa71ef3367..0102d3651009ab274350f142c4376e9d664b994a 100644 (file)
--- a/riscv/insns/mul.h
+++ b/riscv/insns/mul.h
@@ -1 +1,2 @@
+require_extension('M');
 WRITE_RD(sext_xlen(RS1 * RS2));

diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h
index 567e213a42026897c114d3eb2c9e03601c961e8b..051382a96dec4f6489c7eb02a125567a9a992606 100644 (file)
--- a/riscv/insns/mulh.h
+++ b/riscv/insns/mulh.h
@@ -1,3 +1,4 @@
+require_extension('M');
 if (xlen == 64)
   WRITE_RD(mulh(RS1, RS2));
 else

diff --git a/riscv/insns/mulhsu.h b/riscv/insns/mulhsu.h
index 5eeb89c7645c3e7dee3ed3c82f77042107952ef6..c53f90b00118c77326e778d9d0ff4b765bfb2527 100644 (file)
--- a/riscv/insns/mulhsu.h
+++ b/riscv/insns/mulhsu.h
@@ -1,3 +1,4 @@
+require_extension('M');
 if (xlen == 64)
   WRITE_RD(mulhsu(RS1, RS2));
 else

diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h
index ce6a21ed34c8a0f13e512fd40221cccf7f396b00..1ae365080c6c5955f25c406dc2c7e0b76c223770 100644 (file)
--- a/riscv/insns/mulhu.h
+++ b/riscv/insns/mulhu.h
@@ -1,3 +1,4 @@
+require_extension('M');
 if (xlen == 64)
   WRITE_RD(mulhu(RS1, RS2));
 else

diff --git a/riscv/insns/mulw.h b/riscv/insns/mulw.h
index 184dd4126081a42802619258b413031aefa68ba5..ed555452b7a32445a9b8ebcd9477d69821edfcd6 100644 (file)
--- a/riscv/insns/mulw.h
+++ b/riscv/insns/mulw.h
@@ -1,2 +1,3 @@
+require_extension('M');
 require_rv64;
 WRITE_RD(sext32(RS1 * RS2));

diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h
index d074f26f6b5944486a2fd977f73ec999d03dcbce..858799577ccbc4875aa38932455c5d54261b545b 100644 (file)
--- a/riscv/insns/rem.h
+++ b/riscv/insns/rem.h
@@ -1,3 +1,4 @@
+require_extension('M');
 sreg_t lhs = sext_xlen(RS1);
 sreg_t rhs = sext_xlen(RS2);
 if(rhs == 0)

diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h
index c29194732f00d93415df95368052bbef2e3ec4cf..e74774cc23d01baf018971b9b9e75a44d6001025 100644 (file)
--- a/riscv/insns/remu.h
+++ b/riscv/insns/remu.h
@@ -1,3 +1,4 @@
+require_extension('M');
 reg_t lhs = zext_xlen(RS1);
 reg_t rhs = zext_xlen(RS2);
 if(rhs == 0)

diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h
index e4875167e7478985d70c2ab014f69ad5571c4a65..b239c8f32397db74e128e8139bbf028a5a3f004d 100644 (file)
--- a/riscv/insns/remuw.h
+++ b/riscv/insns/remuw.h
@@ -1,3 +1,4 @@
+require_extension('M');
 require_rv64;
 reg_t lhs = zext32(RS1);
 reg_t rhs = zext32(RS2);

diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h
index 2bae1a864683a96b1988caa80a49419c79dda5e4..56221ccd4e742dbe142858d0e7739c182c95818a 100644 (file)
--- a/riscv/insns/remw.h
+++ b/riscv/insns/remw.h
@@ -1,3 +1,4 @@
+require_extension('M');
 require_rv64;
 sreg_t lhs = sext32(RS1);
 sreg_t rhs = sext32(RS2);

diff --git a/riscv/insns/sc_d.h b/riscv/insns/sc_d.h
index 2108079ad1e6d1bda8ecd977777010c04fa12d24..01a45ce9094af383e151d039863e8de6df42d9e3 100644 (file)
--- a/riscv/insns/sc_d.h
+++ b/riscv/insns/sc_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 if (RS1 == p->get_state()->load_reservation)
 {

diff --git a/riscv/insns/sc_w.h b/riscv/insns/sc_w.h
index 729973d478c12486da0c6f3271c2c4da9abd2042..68ec57717aa190ca52e170b4047df859ce69e20d 100644 (file)
--- a/riscv/insns/sc_w.h
+++ b/riscv/insns/sc_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 if (RS1 == p->get_state()->load_reservation)
 {
   MMU.store_uint32(RS1, RS2);

diff --git a/riscv/insns/sltiu.h b/riscv/insns/sltiu.h
index c4478fda14a76d56adebc86c17cd7c4672ec7626..f39845713fbc80eda8acbb8ed83cb6a68b0b7f09 100644 (file)
--- a/riscv/insns/sltiu.h
+++ b/riscv/insns/sltiu.h
@@ -1 +1 @@
-WRITE_RD(RS1 < insn.i_imm());
+WRITE_RD(RS1 < reg_t(insn.i_imm()));

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 2519f84b683fff7e1ac219ed6d8840406d4854fb..e6bbbd44976034be08b8a1253fb092f41d4532a4 100644 (file)
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -4,6 +4,12 @@
 #include "sim.h"
 #include "processor.h"
 
+#define LEVELS(xlen) ((xlen) == 32 ? 2 : 3)
+#define PPN_SHIFT(xlen) ((xlen) == 32 ? 10 : 26)
+#define PTIDXBITS(xlen) ((xlen) == 32 ? 10 : 9)
+#define VPN_BITS(xlen) (PTIDXBITS(xlen) * LEVELS(xlen))
+#define VA_BITS(xlen) (VPN_BITS(xlen) + PGSHIFT)
+
 mmu_t::mmu_t(char* _mem, size_t _memsz)
  : mem(_mem), memsz(_memsz), proc(NULL)
 {
@@ -79,25 +85,26 @@ void* mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch)
   return mem + paddr;
 }
 
-pte_t mmu_t::walk(reg_t addr, bool supervisor, bool store, bool fetch)
+reg_t mmu_t::walk(reg_t addr, bool supervisor, bool store, bool fetch)
 {
-  reg_t msb_mask = -(reg_t(1) << (VA_BITS-1));
+  reg_t msb_mask = -(reg_t(1) << (VA_BITS(proc->xlen) - 1));
   if ((addr & msb_mask) != 0 && (addr & msb_mask) != msb_mask)
     return -1; // address isn't properly sign-extended
 
   reg_t base = proc->get_state()->sptbr;
 
-  int ptshift = (LEVELS-1)*PTIDXBITS;
-  for (reg_t i = 0; i < LEVELS; i++, ptshift -= PTIDXBITS) {
-    reg_t idx = (addr >> (PGSHIFT+ptshift)) & ((1<<PTIDXBITS)-1);
+  int xlen = proc->max_xlen;
+  int ptshift = (LEVELS(xlen) - 1) * PTIDXBITS(xlen);
+  for (reg_t i = 0; i < LEVELS(xlen); i++, ptshift -= PTIDXBITS(xlen)) {
+    reg_t idx = (addr >> (PGSHIFT+ptshift)) & ((1<<PTIDXBITS(xlen))-1);
 
     // check that physical address of PTE is legal
-    reg_t pte_addr = base + idx*sizeof(pte_t);
+    reg_t pte_addr = base + idx*sizeof(reg_t);
     if (pte_addr >= memsz)
       return -1;
 
-    pte_t* ppte = (pte_t*)(mem+pte_addr);
-    reg_t ppn = *ppte >> PTE_PPN_SHIFT;
+    reg_t* ppte = (reg_t*)(mem+pte_addr);
+    reg_t ppn = *ppte >> PPN_SHIFT(xlen);
 
     if ((*ppte & PTE_TYPE) == PTE_TYPE_TABLE) { // next level of page table
       base = ppn << PGSHIFT;

diff --git a/riscv/mmu.h b/riscv/mmu.h
index d6f446bb294c5b91a7b8c5d4a437ed63c6871050..a8853d31a532f2a6c3fc310a984e0f77ad28768e 100644 (file)
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -12,13 +12,8 @@
 #include <vector>
 
 // virtual memory configuration
-typedef reg_t pte_t;
-const reg_t LEVELS = sizeof(pte_t) == 8 ? 3 : 2;
-const reg_t PGSHIFT = 12;
-const reg_t PTIDXBITS = PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2);
+#define PGSHIFT 12
 const reg_t PGSIZE = 1 << PGSHIFT;
-const reg_t VPN_BITS = PTIDXBITS * LEVELS;
-const reg_t VA_BITS = VPN_BITS + PGSHIFT;
 
 struct insn_fetch_t
 {
@@ -153,7 +148,7 @@ private:
   void* refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch);
 
   // perform a page table walk for a given VA; set referenced/dirty bits
-  pte_t walk(reg_t addr, bool supervisor, bool store, bool fetch);
+  reg_t walk(reg_t addr, bool supervisor, bool store, bool fetch);
 
   // translate a virtual address to a physical address
   void* translate(reg_t addr, reg_t bytes, bool store, bool fetch)

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 51e56b1a46629a949de6a151b679ca9540d7dadb..11872656059c93f4556b0b8477b919937904a7ab 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -19,13 +19,17 @@
 #undef STATE
 #define STATE state
 
-processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
-  : sim(_sim), mmu(_mmu), ext(NULL), disassembler(new disassembler_t),
-    id(_id), run(false), debug(false)
+processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
+  : sim(sim), ext(NULL), disassembler(new disassembler_t),
+    id(id), run(false), debug(false)
 {
-  reset(true);
+  parse_isa_string(isa);
+
+  mmu = new mmu_t(sim->mem, sim->memsz);
   mmu->set_processor(this);
 
+  reset(true);
+
   #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
   #include "encoding.h"
   #undef DECLARE_INSN
@@ -44,19 +48,62 @@ processor_t::~processor_t()
   }
 #endif
 
+  delete mmu;
   delete disassembler;
 }
 
+static void bad_isa_string(const char* isa)
+{
+  fprintf(stderr, "error: bad --isa option %s\n", isa);
+  abort();
+}
+
+void processor_t::parse_isa_string(const char* isa)
+{
+  const char* p = isa;
+  const char* all_subsets = "IMAFDC";
+
+  max_xlen = 64;
+  if (strncmp(p, "RV32", 4) == 0)
+    max_xlen = 32, p += 4;
+  else if (strncmp(p, "RV64", 4) == 0)
+    p += 4;
+  else if (strncmp(p, "RV", 2) == 0)
+    p += 2;
+
+  if (!*p)
+    p = all_subsets;
+  else if (*p != 'I')
+    bad_isa_string(isa);
+
+  memset(subsets, 0, sizeof(subsets));
+
+  while (*p) {
+    if (auto next = strchr(all_subsets, *p)) {
+      subsets[(int)*p] = true;
+      all_subsets = next + 1;
+      p++;
+    } else if (*p == 'X') {
+      const char* ext = p+1, *end = ext;
+      while (islower(*end))
+        end++;
+      register_extension(find_extension(std::string(ext, end - ext).c_str())());
+      p = end;
+    } else {
+      bad_isa_string(isa);
+    }
+  }
+
+  if (supports_extension('D') && !supports_extension('F'))
+    bad_isa_string(isa);
+}
+
 void state_t::reset()
 {
   memset(this, 0, sizeof(*this));
   mstatus = set_field(mstatus, MSTATUS_PRV, PRV_M);
   mstatus = set_field(mstatus, MSTATUS_PRV1, PRV_S);
   mstatus = set_field(mstatus, MSTATUS_PRV2, PRV_S);
-#ifdef RISCV_ENABLE_64BIT
-  mstatus = set_field(mstatus, MSTATUS64_UA, UA_RV64);
-  mstatus = set_field(mstatus, MSTATUS64_SA, UA_RV64);
-#endif
   pc = 0x100;
   load_reservation = -1;
 }
@@ -79,7 +126,7 @@ void processor_t::reset(bool value)
     return;
   run = !value;
 
-  state.reset(); // reset the core
+  state.reset();
   set_csr(CSR_MSTATUS, state.mstatus);
 
   if (ext)
@@ -88,7 +135,7 @@ void processor_t::reset(bool value)
 
 void processor_t::raise_interrupt(reg_t which)
 {
-  throw trap_t(((reg_t)1 << 63) | which);
+  throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 }
 
 void processor_t::take_interrupt()
@@ -286,20 +333,19 @@ static bool validate_priv(reg_t priv)
   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 }
 
-static bool validate_arch(reg_t arch)
+static bool validate_arch(int max_xlen, reg_t arch)
 {
-#ifdef RISCV_ENABLE_64BIT
-  if (arch == UA_RV64) return true;
-#endif
+  if (max_xlen == 64 && arch == UA_RV64)
+    return true;
   return arch == UA_RV32;
 }
 
-static bool validate_vm(reg_t vm)
+static bool validate_vm(int max_xlen, reg_t vm)
 {
-  // TODO: VM_SV32 support
-#ifdef RISCV_ENABLE_64BIT
-  if (vm == VM_SV43) return true;
-#endif
+  if (max_xlen == 64 && vm == VM_SV39)
+    return true;
+  if (max_xlen == 32 && vm == VM_SV32)
+    return true;
   return vm == VM_MBARE;
 }
 
@@ -340,7 +386,7 @@ void processor_t::set_csr(int which, reg_t val)
         mask |= MSTATUS_XS;
       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 
-      if (validate_vm(get_field(val, MSTATUS_VM)))
+      if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
         state.mstatus = (state.mstatus & ~MSTATUS_VM) | (val & MSTATUS_VM);
       if (validate_priv(get_field(val, MSTATUS_MPRV)))
         state.mstatus = (state.mstatus & ~MSTATUS_MPRV) | (val & MSTATUS_MPRV);
@@ -352,26 +398,26 @@ void processor_t::set_csr(int which, reg_t val)
         state.mstatus = (state.mstatus & ~MSTATUS_PRV2) | (val & MSTATUS_PRV2);
       if (validate_priv(get_field(val, MSTATUS_PRV3)))
         state.mstatus = (state.mstatus & ~MSTATUS_PRV3) | (val & MSTATUS_PRV3);
-      xlen = 32;
 
       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
-#ifndef RISCV_ENABLE_64BIT
-      state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
-#else
-      state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
-
-      if (validate_arch(get_field(val, MSTATUS64_UA)))
-        state.mstatus = (state.mstatus & ~MSTATUS64_UA) | (val & MSTATUS64_UA);
-      if (validate_arch(get_field(val, MSTATUS64_SA)))
-        state.mstatus = (state.mstatus & ~MSTATUS64_SA) | (val & MSTATUS64_SA);
-      switch (get_field(state.mstatus, MSTATUS_PRV)) {
-        case PRV_U: if (get_field(state.mstatus, MSTATUS64_UA)) xlen = 64; break;
-        case PRV_S: if (get_field(state.mstatus, MSTATUS64_SA)) xlen = 64; break;
-        case PRV_M: xlen = 64; break;
-        default: abort();
+      xlen = 32;
+      if (max_xlen == 32) {
+        state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
+      } else {
+        state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
+
+        if (validate_arch(max_xlen, get_field(val, MSTATUS64_UA)))
+          state.mstatus = (state.mstatus & ~MSTATUS64_UA) | (val & MSTATUS64_UA);
+        if (validate_arch(max_xlen, get_field(val, MSTATUS64_SA)))
+          state.mstatus = (state.mstatus & ~MSTATUS64_SA) | (val & MSTATUS64_SA);
+        switch (get_field(state.mstatus, MSTATUS_PRV)) {
+          case PRV_U: if (get_field(state.mstatus, MSTATUS64_UA)) xlen = 64; break;
+          case PRV_S: if (get_field(state.mstatus, MSTATUS64_SA)) xlen = 64; break;
+          case PRV_M: xlen = 64; break;
+          default: abort();
+        }
       }
-#endif
       break;
     }
     case CSR_SSTATUS:
@@ -458,8 +504,8 @@ reg_t processor_t::get_csr(int which)
     case CSR_STVEC: return state.stvec;
     case CSR_STIMECMP: return state.stimecmp;
     case CSR_SCAUSE:
-      if (xlen == 32 && (state.scause >> 63) != 0)
-        return state.scause | ((reg_t)1 << 31);
+      if (max_xlen > xlen)
+        return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
       return state.scause;
     case CSR_SPTBR: return state.sptbr;
     case CSR_SASID: return 0;

diff --git a/riscv/processor.h b/riscv/processor.h
index e9d9c4fd0ae6675aa2b53ce9933d5465ad4d42db..c0acad9097877703eac19e02b85aedbd603ee948 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -71,7 +71,7 @@ struct state_t
 class processor_t
 {
 public:
-  processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id);
+  processor_t(const char* isa, sim_t* sim, uint32_t id);
   ~processor_t();
 
   void set_debug(bool value);
@@ -86,6 +86,7 @@ public:
   mmu_t* get_mmu() { return mmu; }
   state_t* get_state() { return &state; }
   extension_t* get_extension() { return ext; }
+  bool supports_extension(unsigned char ext) { return subsets[ext]; }
   void push_privilege_stack();
   void pop_privilege_stack();
   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
@@ -100,7 +101,9 @@ private:
   extension_t* ext;
   disassembler_t* disassembler;
   state_t state;
+  bool subsets[256];
   uint32_t id;
+  int max_xlen;
   int xlen;
   bool run; // !reset
   bool debug;
@@ -119,6 +122,7 @@ private:
   friend class mmu_t;
   friend class extension_t;
 
+  void parse_isa_string(const char* isa);
   void build_opcode_map();
   insn_func_t decode_insn(insn_t insn);
 };

diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index 0b095e857f83a0e0ff73d6c221c1dd1b6ce3b605..2a8ee539817b0b7c5b22c96ec96a7eaf0e45110d 100644 (file)
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -1,5 +1,9 @@
 AC_LANG_CPLUSPLUS
 
+AC_SEARCH_LIBS([dlopen], [dl dld], [], [
+  AC_MSG_ERROR([unable to find the dlopen() function])
+])
+
 AC_ARG_WITH([fesvr],
   [AS_HELP_STRING([--with-fesvr],
     [path to your fesvr installation if not in a standard location])],
@@ -13,21 +17,6 @@ AC_CHECK_LIB(fesvr, libfesvr_is_present, [], [AC_MSG_ERROR([libfesvr is required
 
 AC_CHECK_LIB(pthread, pthread_create, [], [AC_MSG_ERROR([libpthread is required])])
 
-AC_ARG_ENABLE([fpu], AS_HELP_STRING([--disable-fpu], [Disable floating-point]))
-AS_IF([test "x$enable_fpu" != "xno"], [
-  AC_DEFINE([RISCV_ENABLE_FPU],,[Define if floating-point instructions are supported])
-])
-
-AC_ARG_ENABLE([rvc], AS_HELP_STRING([--disable-rvc], [Disable RISC-V Compressed]))
-AS_IF([test "x$enable_rvc" != "xno"], [
-  AC_DEFINE([RISCV_ENABLE_RVC],,[Define if RISC-V Compressed is supported])
-])
-
-AC_ARG_ENABLE([64bit], AS_HELP_STRING([--disable-64bit], [Disable 64-bit mode]))
-AS_IF([test "x$enable_64bit" != "xno"], [
-  AC_DEFINE([RISCV_ENABLE_64BIT],,[Define if 64-bit mode is supported])
-])
-                           
 AC_ARG_ENABLE([commitlog], AS_HELP_STRING([--enable-commitlog], [Enable commit log generation]))
 AS_IF([test "x$enable_commitlog" = "xyes"], [
   AC_DEFINE([RISCV_ENABLE_COMMITLOG],,[Enable commit log generation])

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 9e5aa9fa94069401ccc49dcf88cc81a6a2924655..d30725935583f929c8a0017b3dfecf7feb4f3e5b 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -35,6 +35,7 @@ riscv_srcs = \
        mmu.cc \
        disasm.cc \
        extension.cc \
+       extensions.cc \
        rocc.cc \
        regnames.cc \
        $(riscv_gen_srcs) \
@@ -42,7 +43,7 @@ riscv_srcs = \
 riscv_test_srcs =
 
 riscv_gen_hdrs = \
-  icache.h \
+       icache.h \
 
 riscv_gen_srcs = \
        $(addsuffix .cc, $(call get_insn_list,$(src_dir)/riscv/encoding.h))

diff --git a/riscv/sim.cc b/riscv/sim.cc
index 9490af32c6d51b022b8936e9e7adce9ea0daa050..0fdd8297f421f03220ed75d2c4fce1b4dd0a85e5 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -18,7 +18,8 @@ static void handle_signal(int sig)
   signal(sig, &handle_signal);
 }
 
-sim_t::sim_t(size_t nprocs, size_t mem_mb, const std::vector<std::string>& args)
+sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
+             const std::vector<std::string>& args)
   : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
     current_step(0), current_proc(0), debug(false)
 {
@@ -40,20 +41,14 @@ sim_t::sim_t(size_t nprocs, size_t mem_mb, const std::vector<std::string>& args)
 
   debug_mmu = new mmu_t(mem, memsz);
 
-  for (size_t i = 0; i < procs.size(); i++) {
-    procs[i] = new processor_t(this, new mmu_t(mem, memsz), i);
-  }
-
+  for (size_t i = 0; i < procs.size(); i++)
+    procs[i] = new processor_t(isa, this, i);
 }
 
 sim_t::~sim_t()
 {
   for (size_t i = 0; i < procs.size(); i++)
-  {
-    mmu_t* pmmu = procs[i]->get_mmu();
     delete procs[i];
-    delete pmmu;
-  }
   delete debug_mmu;
   free(mem);
 }

diff --git a/riscv/sim.h b/riscv/sim.h
index 9e1362e08343ad5fa20a71abe5b59e31102b118d..ca1ad6f544b9fb100f741f8340ad2d234574625c 100644 (file)
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -15,7 +15,8 @@ class htif_isasim_t;
 class sim_t
 {
 public:
-  sim_t(size_t _nprocs, size_t mem_mb, const std::vector<std::string>& htif_args);
+  sim_t(const char* isa, size_t _nprocs, size_t mem_mb,
+        const std::vector<std::string>& htif_args);
   ~sim_t();
 
   // run the simulation to completion
@@ -72,6 +73,7 @@ private:
   reg_t get_tohost(const std::vector<std::string>& args);
 
   friend class htif_isasim_t;
+  friend class processor_t;
 };
 
 extern volatile bool ctrlc_pressed;

diff --git a/spike_main/extensions.cc b/spike_main/extensions.cc
deleted file mode 100644 (file)
index 315621f..0000000
--- a/spike_main/extensions.cc
+++ /dev/null
@@ -1,35 +0,0 @@
-#include "extension.h"
-#include <string>
-#include <map>
-#include <dlfcn.h>
-
-static std::map<std::string, std::function<extension_t*()>>& extensions()
-{
-  static std::map<std::string, std::function<extension_t*()>> v;
-  return v;
-}
-
-void register_extension(const char* name, std::function<extension_t*()> f)
-{
-  extensions()[name] = f;
-}
-
-std::function<extension_t*()> find_extension(const char* name)
-{
-  if (!extensions().count(name)) {
-    // try to find extension xyz by loading libxyz.so
-    std::string libname = std::string("lib") + name + ".so";
-    if (!dlopen(libname.c_str(), RTLD_LAZY)) {
-      fprintf(stderr, "couldn't find extension '%s' (or library '%s')\n",
-              name, libname.c_str());
-      exit(-1);
-    }
-    if (!extensions().count(name)) {
-      fprintf(stderr, "couldn't find extension '%s' in shared library '%s'\n",
-              name, libname.c_str());
-      exit(-1);
-    }
-  }
-
-  return extensions()[name];
-}

diff --git a/spike_main/spike.cc b/spike_main/spike.cc
index ab5cea554957a97e388e7d71e351c94f8bffb332..7a85bd17798554dea16ff4b0447e142a923667d2 100644 (file)
--- a/spike_main/spike.cc
+++ b/spike_main/spike.cc
@@ -17,11 +17,12 @@ static void help()
 {
   fprintf(stderr, "usage: spike [host options] <target program> [target options]\n");
   fprintf(stderr, "Host Options:\n");
-  fprintf(stderr, "  -p <n>             Simulate <n> processors\n");
-  fprintf(stderr, "  -m <n>             Provide <n> MB of target memory\n");
+  fprintf(stderr, "  -p <n>             Simulate <n> processors [default 1]\n");
+  fprintf(stderr, "  -m <n>             Provide <n> MiB of target memory [default 4096]\n");
   fprintf(stderr, "  -d                 Interactive debug mode\n");
   fprintf(stderr, "  -g                 Track histogram of PCs\n");
   fprintf(stderr, "  -h                 Print this help message\n");
+  fprintf(stderr, "  --isa=<name>       RISC-V ISA string [default RV64IMAFDC]\n");
   fprintf(stderr, "  --ic=<S>:<W>:<B>   Instantiate a cache model with S sets,\n");
   fprintf(stderr, "  --dc=<S>:<W>:<B>     W ways, and B-byte blocks (with S and\n");
   fprintf(stderr, "  --l2=<S>:<W>:<B>     B both powers of 2).\n");
@@ -40,6 +41,7 @@ int main(int argc, char** argv)
   std::unique_ptr<dcache_sim_t> dc;
   std::unique_ptr<cache_sim_t> l2;
   std::function<extension_t*()> extension;
+  const char* isa = "RV64";
 
   option_parser_t parser;
   parser.help(&help);
@@ -51,6 +53,7 @@ int main(int argc, char** argv)
   parser.option(0, "ic", 1, [&](const char* s){ic.reset(new icache_sim_t(s));});
   parser.option(0, "dc", 1, [&](const char* s){dc.reset(new dcache_sim_t(s));});
   parser.option(0, "l2", 1, [&](const char* s){l2.reset(cache_sim_t::construct(s, "L2$"));});
+  parser.option(0, "isa", 1, [&](const char* s){isa = s;});
   parser.option(0, "extension", 1, [&](const char* s){extension = find_extension(s);});
   parser.option(0, "extlib", 1, [&](const char *s){
     void *lib = dlopen(s, RTLD_NOW | RTLD_GLOBAL);
@@ -64,7 +67,7 @@ int main(int argc, char** argv)
   if (!*argv1)
     help();
   std::vector<std::string> htif_args(argv1, (const char*const*)argv + argc);
-  sim_t s(nprocs, mem_mb, htif_args);
+  sim_t s(isa, nprocs, mem_mb, htif_args);
 
   if (ic && l2) ic->set_miss_handler(&*l2);
   if (dc && l2) dc->set_miss_handler(&*l2);

diff --git a/spike_main/spike_main.ac b/spike_main/spike_main.ac
index b913c35288422273d4009b86835293da95badbe4..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
--- a/spike_main/spike_main.ac
+++ b/spike_main/spike_main.ac
@@ -1,3 +0,0 @@
-AC_SEARCH_LIBS([dlopen], [dl dld], [], [
-  AC_MSG_ERROR([unable to find the dlopen() function])
-])

diff --git a/spike_main/spike_main.mk.in b/spike_main/spike_main.mk.in
index dd67998c1b60af93170b15fb19d71183ab78402e..500446fa6ce6fed8ccef37196c9ea8847bb28a98 100644 (file)
--- a/spike_main/spike_main.mk.in
+++ b/spike_main/spike_main.mk.in
@@ -11,4 +11,3 @@ spike_main_install_prog_srcs = \
 spike_main_hdrs = \
 
 spike_main_srcs = \
-  extensions.cc \