add sv addi predicated unit test, including inversion and zeroing

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index d77287403e2c96b1a2b4c2c14773bed78751a4d4..22eb2b17db9d5e893856165c12c91f68176f15cd 100644 (file)
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -8,7 +8,12 @@
         li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ); \
         csrrw  x0, 0x4c0, x1
 
+#define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, active ) \
+        li     x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, active ); \
+        csrrw  x0, 0x4c8, x1
+
 #define CLR_SV_CSRS( ) csrrw   x0, 0x4c0, 0
+#define CLR_SV_PRED_CSRS( ) csrrw   x0, 0x4c8, 0
 
 #define SET_SV_MVL( val ) csrrwi   x0, 0x4f2, val
 #define SET_SV_VL( val )  csrrwi   x0, 0x4f0, val

diff --git a/isa/rv64ui/Makefrag.sv b/isa/rv64ui/Makefrag.sv
index eac21e2c9c2d3acfed1429585ec2378bf241bb8a..9e79ca5c98f1baf73212b639f537e1bb591b4892 100644 (file)
--- a/isa/rv64ui/Makefrag.sv
+++ b/isa/rv64ui/Makefrag.sv
@@ -6,6 +6,7 @@ rv64ui_sv_tests = \
        sv_addi \
        sv_addi_redirect \
        sv_addi_scalar_src \
+       sv_addi_predicated \
 
 rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sv_tests))
 rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sv_tests))

diff --git a/isa/rv64ui/sv_addi_predicated.S b/isa/rv64ui/sv_addi_predicated.S
new file mode 100644 (file)
index 0000000..32902f0
--- /dev/null
+++ b/isa/rv64ui/sv_addi_predicated.S
@@ -0,0 +1,87 @@
+#include "riscv_test.h"
+#include "sv_test_macros.h"
+
+RVTEST_RV64U        # Define TVM used by program.
+
+#define SV_PREDICATION_TEST( pred, inv, zero, expect1, expect2 ) \
+                                                        \
+        SV_LD_DATA( x2, testdata   , 0);               \
+        SV_LD_DATA( x3, testdata+8 , 0);               \
+        SV_LD_DATA( x4, testdata+16, 0);               \
+        SV_LD_DATA( x5, testdata+24, 0);               \
+                                                        \
+        li      x6, pred;                               \
+                                                        \
+        SET_SV_MVL( 2);                                  \
+        SET_SV_CSR( 1, 3, 0, 3, 1, 0);                   \
+        SET_SV_PRED_CSR( 1, 3, zero, inv, 6, 1);         \
+        SET_SV_VL( 2);                                   \
+                                                        \
+        addi    x3, x3, 1;                              \
+                                                        \
+        CLR_SV_CSRS();                                  \
+        SET_SV_VL( 0);                                   \
+        SET_SV_MVL( 0);                                  \
+                                                        \
+        TEST_SV_IMM( x2, 1001);                         \
+        TEST_SV_IMM( x3, expect1);                       \
+        TEST_SV_IMM( x4, expect2);                       \
+        TEST_SV_IMM( x5, 1002);
+
+
+# SV test: vector-vector add
+#
+# sets up x3 and x4 with data, sets VL to 2, and carries out
+# an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
+
+# Test code region.
+RVTEST_CODE_BEGIN   # Start of test code.
+
+        # no zeroing, no inversion
+        SV_PREDICATION_TEST( 0x1, 0, 0, 42, 42 ) 
+        SV_PREDICATION_TEST( 0x2, 0, 0, 41, 43 ) 
+        SV_PREDICATION_TEST( 0x3, 0, 0, 42, 43 ) 
+        SV_PREDICATION_TEST( 0x0, 0, 0, 41, 42 ) 
+
+        # zeroing, no inversion
+        SV_PREDICATION_TEST( 0x1, 0, 1, 42, 0 ) 
+        SV_PREDICATION_TEST( 0x2, 0, 1, 0, 43 ) 
+        SV_PREDICATION_TEST( 0x3, 0, 1, 42, 43 ) 
+        SV_PREDICATION_TEST( 0x0, 0, 1, 0, 0 ) 
+
+        # no zeroing, inversion
+        SV_PREDICATION_TEST( 0x2, 1, 0, 42, 42 ) 
+        SV_PREDICATION_TEST( 0x1, 1, 0, 41, 43 ) 
+        SV_PREDICATION_TEST( 0x0, 1, 0, 42, 43 ) 
+        SV_PREDICATION_TEST( 0x3, 1, 0, 41, 42 ) 
+
+        # zeroing, inversion
+        SV_PREDICATION_TEST( 0x2, 1, 1, 42, 0 ) 
+        SV_PREDICATION_TEST( 0x1, 1, 1, 0, 43 ) 
+        SV_PREDICATION_TEST( 0x0, 1, 1, 42, 43 ) 
+        SV_PREDICATION_TEST( 0x3, 1, 1, 0, 0 ) 
+
+        RVTEST_PASS           # Signal success.
+fail:
+        RVTEST_FAIL
+RVTEST_CODE_END     # End of test code.
+
+# Input data section.
+# This section is optional, and this data is NOT saved in the output.
+.data
+        .align 3
+testdata:
+        .dword 1001
+        .dword 41
+        .dword 42
+        .dword 1002
+
+# Output data section.
+RVTEST_DATA_BEGIN   # Start of test output data region.
+        .align 3
+result:
+        .dword -1
+        .dword -1
+        .dword -1
+RVTEST_DATA_END     # End of test output data region.
+