(no commit message)

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index 2de8a773a9e023c36d6d69ad29830a848ffe3c8b..ee2b9034b16557a27e98e9f3710aee1f1031c1f2 100644 (file)
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -22,14 +22,18 @@ Checklist based on above
 
 If you violate any of the above stated hard-and-fast rules you will end up learning the hard way by **DESTROYING** the FPGA.
 
+To start we have to ensure we have a safe set up.
+
+* Ensure power is disconnected from FPGA
+* Ensure STLINKV2 USB is disconnected
+* Ensure FPGA USB is disconnected
+
 | Done?   | Checklist Step |
 |---------|----------------|
-|         | Ensure there are **NO** wires connected to either the FPGA or the STLINKv2 |
 |         | Review the STLINKv2 Connector diagram and table |
 |         | Review the connections table for your model of fpga |
-|         | Ensure there are **ZERO** wires connected to either the FPGA or the STLINKv2, there should not even be a usb, mirco-usb, or power cable anywhere these components |
 |         | Make sure the orientation of your FPGA board and your STLINKv2 are the same as the images and diagrams on this page |
-|         | Wire each of the coloured jumper cables to the corresponding pins on the FPGA and the STLINKv2 according to the diagrams, tables, and images on this page |
+|         | Wire each of the coloured jumper cables to the corresponding pins on the FPGA and the STLINKv2 according to the diagrams, tables, and images on this page. Below are separate checklist for each model of FPGA |
 
 Follow this section if you have the ULX3S FPGA:
 
@@ -58,7 +62,8 @@ Final steps for both FPGA boards:
 | Done?   | Checklist Step |
 |---------|----------------|
 |         | Check each jumper wire connection between the corresponding pins on the FPGA and the STLINKv2 **THREE** times |
-|         | I don't know what's next, need to review with lkcl |
+|         | ***lckl*** check for ground loops? |
+
 
 ## Connecting the dots: