Yet more tests of m32r instructions

diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog
index 71a5158cc28e44f2a6d6be3b8067505cd032a392..b113ba77f2f2558a76f3b2964bc012efcdee2e8e 100644 (file)
--- a/sim/testsuite/ChangeLog
+++ b/sim/testsuite/ChangeLog
@@ -1,5 +1,11 @@
 Thu Feb 19 11:15:45 1998  Nick Clifton  <nickc@cygnus.com>
 
+       * sim/m32r/or3.cgs: Test OR3 instruction.
+       * sim/m32r/rach.cgs: Test RACH instruction.
+       * sim/m32r/rem.cgs: Test REM instruction.
+       * sim/m32r/sub.cgs: Test SUB instruction.
+       * sim/m32r/mv.cgs: Test MV instruction.
+       * sim/m32r/mul.cgs: Test MUL instruction.
        * sim/m32r/bl24.cgs: Test long BL instruction.
        * sim/m32r/bl8.cgs: Test short BL instruction.
        * sim/m32r/blez.cgs: Test BLEZ instruction.
@@ -44,6 +50,7 @@ start-sanitize-m342rx
        * sim/m32r/bncl24.cgs: Test long BNCL instruction.
        * sim/m32r/bncl8.cgs: Test short BNCL instruction.
        * sim/m32r/divh.cgs: Test DIVH instruction.
+       * sim/m32r/rach-dsi.cgs: Test extended RACH instruction.
 end-sanitize-m342rx    
 Tue Feb 17 12:46:05 1998  Doug Evans  <devans@seba.cygnus.com>