Applying #9044c10 changes in LiteDRAM (phy/ecp5ddrphy: use sys_rst instead of sys2x_r...

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index a1e66c304f89ad6eff152b0d66cbb004f19dc2d2..0ad4e23d066bc14124c0ebd2cd0d1d20dc908a42 100644 (file)
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -23,28 +23,25 @@ from gram.compat import Timeline
 
 
 class ECP5DDRPHYInit(Elaboratable):
-    def __init__(self, eclk_cd):
+    def __init__(self):
         self.pause = Signal()
         self.stop = Signal()
         self.delay = Signal()
-        self._eclk_cd = eclk_cd
+        self.reset = Signal()
 
     def elaborate(self, platform):
         m = Module()
 
         new_lock = Signal()
         update = Signal()
-        stop = Signal()
         freeze = Signal()
-        pause = Signal()
-        reset = Signal()
 
         # DDRDLLA instance -------------------------------------------------------------------------
         _lock = Signal()
         delay = Signal()
         m.submodules += Instance("DDRDLLA",
                                  i_CLK=ClockSignal("sync2x"),
-                                 i_RST=ResetSignal(),
+                                 i_RST=ResetSignal("init"),
                                  i_UDDCNTLN=~update,
                                  i_FREEZE=freeze,
                                  o_DDRDEL=delay,
@@ -52,34 +49,29 @@ class ECP5DDRPHYInit(Elaboratable):
                                  )
         lock = Signal()
         lock_d = Signal()
-        m.submodules += FFSynchronizer(_lock, lock)
-        m.d.sync += lock_d.eq(lock)
+        m.submodules += FFSynchronizer(_lock, lock, o_domain="init")
+        m.d.init += lock_d.eq(lock)
         m.d.sync += new_lock.eq(lock & ~lock_d)
 
         # DDRDLLA/DDQBUFM/ECLK initialization sequence ---------------------------------------------
         t = 8  # in cycles
         tl = Timeline([
             (1*t,  [freeze.eq(1)]),  # Freeze DDRDLLA
-            (2*t,  [stop.eq(1)]),   # Stop ECLK domain
-            (3*t,  [reset.eq(1)]),  # Reset ECLK domain
-            (4*t,  [reset.eq(0)]),  # Release ECLK domain reset
-            (5*t,  [stop.eq(0)]),   # Release ECLK domain stop
+            (2*t,  [self.stop.eq(1)]),   # Stop ECLK domain
+            (3*t,  [self.reset.eq(1)]),  # Reset ECLK domain
+            (4*t,  [self.reset.eq(0)]),  # Release ECLK domain reset
+            (5*t,  [self.stop.eq(0)]),   # Release ECLK domain stop
             (6*t,  [freeze.eq(0)]),  # Release DDRDLLA freeze
-            (7*t,  [pause.eq(1)]),  # Pause DQSBUFM
+            (7*t,  [self.pause.eq(1)]),  # Pause DQSBUFM
             (8*t,  [update.eq(1)]),  # Update DDRDLLA
             (9*t,  [update.eq(0)]),  # Release DDRDMMA update
-            (10*t, [pause.eq(0)]),  # Release DQSBUFM pause
+            (10*t, [self.pause.eq(0)]),  # Release DQSBUFM pause
         ])
         m.submodules += tl
         # Wait DDRDLLA Lock
         m.d.comb += tl.trigger.eq(new_lock)
 
-        m.d.comb += [
-            self.pause.eq(pause),
-            self.stop.eq(stop),
-            self.delay.eq(delay),
-            ResetSignal(self._eclk_cd).eq(reset)
-        ]
+        m.d.comb += self.delay.eq(delay)
 
         return m
 
@@ -164,7 +156,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         bankbits = len(self.pads.ba.o)
 
         # Init -------------------------------------------------------------------------------------
-        m.submodules.init = init = DomainRenamer("init")(ECP5DDRPHYInit("sync2x"))
+        m.submodules.init = init = ECP5DDRPHYInit()
 
         # Parameters -------------------------------------------------------------------------------
         cl, cwl = get_cl_cw("DDR3", tck)
@@ -184,7 +176,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         for i in range(len(self.pads.clk.o)):
             sd_clk_se = Signal()
             m.submodules += Instance("ODDRX2F",
-                                     i_RST=ResetSignal("sync2x"),
+                                     i_RST=ResetSignal("sync"),
                                      i_ECLK=ClockSignal("sync2x"),
                                      i_SCLK=ClockSignal(),
                                      i_D0=0,
@@ -197,7 +189,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         # Addresses and Commands ---------------------------------------------------------------
         for i in range(addressbits):
             m.submodules += Instance("ODDRX2F",
-                                     i_RST=ResetSignal("sync2x"),
+                                     i_RST=ResetSignal("sync"),
                                      i_ECLK=ClockSignal("sync2x"),
                                      i_SCLK=ClockSignal(),
                                      i_D0=dfi.phases[0].address[i],
@@ -208,7 +200,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                                      )
         for i in range(bankbits):
             m.submodules += Instance("ODDRX2F",
-                                     i_RST=ResetSignal("sync2x"),
+                                     i_RST=ResetSignal("sync"),
                                      i_ECLK=ClockSignal("sync2x"),
                                      i_SCLK=ClockSignal(),
                                      i_D0=dfi.phases[0].bank[i],
@@ -225,7 +217,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         for name in controls:
             for i in range(len(getattr(self.pads, name))):
                 m.submodules += Instance("ODDRX2F",
-                                         i_RST=ResetSignal("sync2x"),
+                                         i_RST=ResetSignal("sync"),
                                          i_ECLK=ClockSignal("sync2x"),
                                          i_SCLK=ClockSignal(),
                                          i_D0=getattr(dfi.phases[0], name)[i],
@@ -287,7 +279,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                                      # Clocks / Reset
                                      i_SCLK=ClockSignal("sync"),
                                      i_ECLK=ClockSignal("sync2x"),
-                                     i_RST=ResetSignal("sync2x"),
+                                     i_RST=ResetSignal("sync"),
                                      i_DDRDEL=init.delay,
                                      i_PAUSE=init.pause | self._dly_sel.w_data[i],
 
@@ -350,9 +342,9 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                 with m.Case(1):
                     m.d.sync += dm_o_data_muxed.eq(dm_o_data_d[4:])
             m.submodules += Instance("ODDRX2DQA",
-                                     i_RST=ResetSignal("sync2x"),
+                                     i_RST=ResetSignal("sync"),
                                      i_ECLK=ClockSignal("sync2x"),
-                                     i_SCLK=ClockSignal(),
+                                     i_SCLK=ClockSignal("sync"),
                                      i_DQSW270=dqsw270,
                                      i_D0=dm_o_data_muxed[0],
                                      i_D1=dm_o_data_muxed[1],
@@ -365,7 +357,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
             dqs_oe_n = Signal()
             m.submodules += [
                 Instance("ODDRX2DQSB",
-                         i_RST=ResetSignal("sync2x"),
+                         i_RST=ResetSignal("sync"),
                          i_ECLK=ClockSignal("sync2x"),
                          i_SCLK=ClockSignal(),
                          i_DQSW=dqsw,
@@ -376,7 +368,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                          o_Q=dqs
                          ),
                 Instance("TSHX2DQSA",
-                         i_RST=ResetSignal("sync2x"),
+                         i_RST=ResetSignal("sync"),
                          i_ECLK=ClockSignal("sync2x"),
                          i_SCLK=ClockSignal(),
                          i_DQSW=dqsw,
@@ -425,7 +417,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                 _dq_i_data = Signal(4)
                 m.submodules += [
                     Instance("ODDRX2DQA",
-                             i_RST=ResetSignal("sync2x"),
+                             i_RST=ResetSignal("sync"),
                              i_ECLK=ClockSignal("sync2x"),
                              i_SCLK=ClockSignal(),
                              i_DQSW270=dqsw270,
@@ -444,7 +436,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                              o_Z=dq_i_delayed
                              ),
                     Instance("IDDRX2DQA",
-                             i_RST=ResetSignal("sync2x"),
+                             i_RST=ResetSignal("sync"),
                              i_ECLK=ClockSignal("sync2x"),
                              i_SCLK=ClockSignal(),
                              i_DQSR90=dqsr90,
@@ -475,7 +467,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                 ]
                 m.submodules += [
                     Instance("TSHX2DQA",
-                             i_RST=ResetSignal("sync2x"),
+                             i_RST=ResetSignal("sync"),
                              i_ECLK=ClockSignal("sync2x"),
                              i_SCLK=ClockSignal(),
                              i_DQSW270=dqsw270,