Fix another stupid bug in the same line

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 9af4ce047d79ed08e8a137be515734a43122d2ad..cde72a8e3e196eeafd47425127848b7b1b240c6f 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -824,7 +824,7 @@ struct VerificImporter
 
                                SigBit outsig = net_map.at(out);
                                log_assert(outsig.wire && GetSize(outsig.wire) == 1);
-                               outsig.wire->attributes["\\init"] = Const(0, 1);
+                               outsig.wire->attributes["\\init"] = Const(1, 1);
 
                                module->addDff(NEW_ID, net_map.at(clk), net_map.at(in2), net_map.at(out));
                                continue;