Merge pull request #874 from YosysHQ/clifford/andopt

Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 26a3ca7bc00948fc151c46cc47940115cd6377a7..a05db2a4fdf86d72a1ab75f4fcb9dfc6a19987af 100644 (file)
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -155,6 +155,13 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
                        new_b.append_bit(it.first.second);
                }
 
+               if (cell->type.in("$and", "$or") && i == GRP_CONST_A) {
+                       log("  Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a));
+                       module->connect(new_y, new_b);
+                       module->connect(new_conn);
+                       continue;
+               }
+
                RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
 
                c->setPort("\\A", new_a);