stats: x86: updates due to patch on vex
authorNilay Vaish <nilay@cs.wisc.edu>
Sat, 18 Jul 2015 20:07:35 +0000 (15:07 -0500)
committerNilay Vaish <nilay@cs.wisc.edu>
Sat, 18 Jul 2015 20:07:35 +0000 (15:07 -0500)
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt

index 9f38e11f8818f50c0dbf3a065da39aefa2cf0fb6..ce7843f5cc19171dbf18b7948a816edaa218fa8f 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.130109                       # Number of seconds simulated
-sim_ticks                                5130108675000                       # Number of ticks simulated
-final_tick                               5130108675000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.154115                       # Number of seconds simulated
+sim_ticks                                5154115247000                       # Number of ticks simulated
+final_tick                               5154115247000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 172691                       # Simulator instruction rate (inst/s)
-host_op_rate                                   341343                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2172133567                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 759908                       # Number of bytes of host memory used
-host_seconds                                  2361.78                       # Real time elapsed on the host
-sim_insts                                   407858109                       # Number of instructions simulated
-sim_ops                                     806179275                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 128017                       # Simulator instruction rate (inst/s)
+host_op_rate                                   253040                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1617614851                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 806232                       # Number of bytes of host memory used
+host_seconds                                  3186.24                       # Real time elapsed on the host
+sim_insts                                   407894468                       # Number of instructions simulated
+sim_ops                                     806246903                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         4288                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         4480                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1044544                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10779584                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1047104                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10813376                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11857088                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1044544                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1044544                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9583168                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9583168                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           67                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             11893632                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1047104                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1047104                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9584064                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9584064                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker           70                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              16321                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             168431                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              16361                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             168959                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                185267                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          149737                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               149737                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            836                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                185838                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          149751                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               149751                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            869                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               203611                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2101239                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide         5527                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2311274                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          203611                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             203611                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1868024                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1868024                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1868024                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           836                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               203159                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2098008                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide         5501                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2307599                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          203159                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             203159                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1859497                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1859497                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1859497                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           869                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              203611                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2101239                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide         5527                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4179299                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        185267                       # Number of read requests accepted
-system.physmem.writeReqs                       149737                       # Number of write requests accepted
-system.physmem.readBursts                      185267                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     149737                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11846656                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     10432                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9581440                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11857088                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                9583168                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      163                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu.inst              203159                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2098008                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide         5501                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4167097                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        185838                       # Number of read requests accepted
+system.physmem.writeReqs                       149751                       # Number of write requests accepted
+system.physmem.readBursts                      185838                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     149751                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11883456                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10176                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   9582144                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11893632                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                9584064                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      159                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          48775                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11590                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11256                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12288                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11911                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               11840                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11665                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10867                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10808                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               11222                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11056                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11302                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11775                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11547                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12196                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11932                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11849                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               10246                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9545                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9025                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8913                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9024                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9097                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8779                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8697                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8886                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9043                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9545                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9380                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9802                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9849                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              10052                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               9827                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          48492                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11738                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11323                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11916                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11912                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               12271                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11705                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10605                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10992                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               11596                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11415                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11752                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11610                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11474                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12022                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11655                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11693                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10141                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9357                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8826                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8882                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9347                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9205                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8767                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8936                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9149                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                9192                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              10057                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9346                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9689                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               9578                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               9663                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9586                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5130108625500                       # Total gap between requests
+system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5154115197500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  185267                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  185838                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 149737                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    170610                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     11668                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2033                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       465                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        56                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 149751                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    171307                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     11621                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      1958                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       473                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        54                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                        33                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                        30                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        36                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        29                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        30                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       23                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       23                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -156,301 +156,303 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2238                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2978                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     7955                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     7943                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7727                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7753                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7793                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     9624                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     9979                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    11771                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    10405                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9975                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8508                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9054                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2253                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2875                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7881                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     7883                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7770                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     7889                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7857                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     9606                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     9971                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11760                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    10283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9854                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8546                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9083                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     9183                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                     7802                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7701                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7621                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      257                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      246                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      212                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      195                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      210                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      220                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7680                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7594                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      297                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      249                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      194                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      177                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        9                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        72239                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      296.626919                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     176.108811                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     319.147383                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          27668     38.30%     38.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17613     24.38%     62.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         7498     10.38%     73.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         4242      5.87%     78.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2823      3.91%     82.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1928      2.67%     85.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1515      2.10%     87.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1131      1.57%     89.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7821     10.83%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          72239                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7351                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.179159                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      561.374907                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           7350     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::45                      144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      131                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       87                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       48                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       26                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        72428                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      296.370685                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     175.530831                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     319.820481                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          27904     38.53%     38.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17658     24.38%     62.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         7456     10.29%     73.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         4108      5.67%     78.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2731      3.77%     82.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1986      2.74%     85.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1581      2.18%     87.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1174      1.62%     89.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7830     10.81%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          72428                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7352                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.252992                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      561.335686                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           7351     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7351                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7351                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.365937                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.603384                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.112022                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            6287     85.53%     85.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              96      1.31%     86.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             185      2.52%     89.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              82      1.12%     90.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             111      1.51%     91.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             202      2.75%     94.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              31      0.42%     95.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              14      0.19%     95.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              14      0.19%     95.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              10      0.14%     95.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               9      0.12%     95.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               5      0.07%     95.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             246      3.35%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               8      0.11%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.05%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               8      0.11%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               2      0.03%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.01%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             7      0.10%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.01%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.03%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             2      0.03%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            14      0.19%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.01%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             2      0.03%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.03%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             3      0.04%     99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            7352                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7352                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.364663                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.601623                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       13.168660                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            6294     85.61%     85.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              82      1.12%     86.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             194      2.64%     89.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              86      1.17%     90.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              99      1.35%     91.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             218      2.97%     94.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              33      0.45%     95.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              11      0.15%     95.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              15      0.20%     95.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               6      0.08%     95.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               3      0.04%     95.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               3      0.04%     95.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             253      3.44%     99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.07%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               3      0.04%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               7      0.10%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               4      0.05%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.03%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.04%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.01%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.04%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            15      0.20%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.03%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             2      0.03%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.03%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.01%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::196-199             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7351                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1992019456                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5462719456                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    925520000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10761.62                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total            7352                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2003475850                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5484957100                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    928395000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10790.00                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29511.62                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  29540.00                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.31                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.87                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.86                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.31                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.87                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.86                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.79                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     151846                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    110728                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.16                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     152313                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    110658                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   82.03                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.95                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15313574.24                       # Average gap between requests
-system.physmem.pageHitRate                      78.42                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  269393040                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  146990250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 719355000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                475152480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           335073401520                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           129448929735                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           2964510370500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             3430643592525                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.727957                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   4931666056220                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    171305420000                       # Time in different power states
+system.physmem.writeRowHitRate                  73.89                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15358415.20                       # Average gap between requests
+system.physmem.pageHitRate                      78.40                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  270738720                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  147724500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 721203600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                476027280                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           336641292000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           130240416060                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           2978219081250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             3446716483410                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.731853                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   4954469478230                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    172107000000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     27131976280                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     27531969270                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  276733800                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  150995625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 724448400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                494968320                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           335073401520                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           129698055360                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           2964291831000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             3430710434025                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.740988                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   4931307220986                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    171305420000                       # Time in different power states
+system.physmem_1.actEnergy                  276816960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  151041000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 727084800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                494164800                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           336641292000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           130162900905                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           2978287085250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             3446740385715                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.736489                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   4954592740478                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    172107000000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     27495924014                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     27415396022                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                86802866                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          86802866                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            898884                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             79915985                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                78142205                       # Number of BTB hits
+system.cpu.branchPred.lookups                86789700                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          86789700                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            894071                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             80040540                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                78122239                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.780444                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1557172                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             181109                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.603338                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1558682                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             180590                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                        449354840                       # number of cpu cycles simulated
+system.cpu.numCycles                        449504376                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           27419696                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      428691862                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    86802866                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           79699377                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     417944649                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1884104                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     141232                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                57475                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        210217                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles           60                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          747                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9135683                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                451645                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5364                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          446716128                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.893620                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.051973                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           27485279                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      428718572                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    86789700                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           79680921                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     418030666                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1875632                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     150798                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                59488                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        208856                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles           90                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          672                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9123295                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                449746                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    4755                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          446873665                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.892893                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.051645                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                281460190     63.01%     63.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2138894      0.48%     63.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 72152839     16.15%     79.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1576063      0.35%     79.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2129707      0.48%     80.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2325949      0.52%     80.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1505469      0.34%     81.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1859854      0.42%     81.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 81567163     18.26%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                281625965     63.02%     63.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2138685      0.48%     63.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72155487     16.15%     79.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1568927      0.35%     80.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2122343      0.47%     80.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2325830      0.52%     80.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1507660      0.34%     81.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1867139      0.42%     81.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 81561629     18.25%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            446716128                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.193172                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.954016                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 22817532                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             264818622                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 150719822                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               7418100                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 942052                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              837890793                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                 942052                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 25656597                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               222831809                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       12884327                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 154608390                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              29792953                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              834381209                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                449377                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               12218260                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 146025                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               14738284                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           996692347                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1812155414                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1113986633                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               357                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             964101925                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 32590420                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             461964                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         466029                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  38550499                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             17267645                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10120270                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1295034                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1078818                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  828854264                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1188467                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 823634023                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            239226                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        23863451                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     35922872                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         148640                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     446716128                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.843753                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.418621                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            446873665                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.193079                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.953758                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 22890187                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             264923803                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 150702566                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               7419293                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 937816                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              837865741                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                 937816                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 25728184                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               222903682                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       12889746                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 154594835                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              29819402                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              834359795                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                448369                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               12212745                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 141423                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               14773604                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           996662587                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1812180036                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1114009606                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               309                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             964181963                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 32480622                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             461875                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         465908                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  38538990                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             17255328                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10136845                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1286418                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1053742                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  828858399                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1188333                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 823669123                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            243637                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        23799824                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     35821203                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         147900                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     446873665                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.843181                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.418517                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           262749029     58.82%     58.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            13824325      3.09%     61.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             9784338      2.19%     64.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7058515      1.58%     65.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            74344613     16.64%     82.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4389971      0.98%     83.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72797188     16.30%     99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1191150      0.27%     99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              576999      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           262902763     58.83%     58.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            13828746      3.09%     61.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             9781500      2.19%     64.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7055144      1.58%     65.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            74339132     16.64%     82.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4387820      0.98%     83.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            72808347     16.29%     99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1195469      0.27%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              574744      0.13%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       446716128                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       446873665                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1965794     71.96%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     71.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 607707     22.24%     94.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                158405      5.80%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1974081     71.95%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     2      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     71.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 609151     22.20%     94.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                160307      5.84%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            286388      0.03%      0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             795396124     96.57%     96.61% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               150331      0.02%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                127202      0.02%     96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            285084      0.03%      0.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             795424559     96.57%     96.61% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               150449      0.02%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                127671      0.02%     96.64% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.64% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                  98      0.00%     96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                  84      0.00%     96.64% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.64% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.64% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.64% # Type of FU issued
@@ -474,98 +476,98 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.64% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.64% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.64% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             18333764      2.23%     98.87% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9340116      1.13%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             18333357      2.23%     98.87% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9347919      1.13%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              823634023                       # Type of FU issued
-system.cpu.iq.rate                           1.832926                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2731906                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.003317                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2096954851                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         853918294                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    819080568                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 454                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                494                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          158                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              826079323                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     218                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1864091                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              823669123                       # Type of FU issued
+system.cpu.iq.rate                           1.832394                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2743541                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.003331                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2097198642                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         853858757                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    819128971                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 446                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                432                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          155                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              826127364                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     216                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1863869                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3276332                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        15288                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        14318                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1695886                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      3260732                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        15309                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        14369                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1707925                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2207587                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         71306                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2207612                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         70919                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 942052                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               204779875                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               9950427                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           830042731                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            154301                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              17267645                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             10120270                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             698404                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 395340                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               8703386                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          14318                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         517416                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       531852                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1049268                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             822011733                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              17933627                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1492341                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 937816                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               204799790                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles              10007204                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           830046732                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            155850                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              17255344                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             10136845                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             698572                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 395239                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               8760495                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          14369                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         514805                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       529588                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1044393                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             822053660                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              17935902                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1483234                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     27049256                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 83240327                       # Number of branches executed
-system.cpu.iew.exec_stores                    9115629                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.829315                       # Inst execution rate
-system.cpu.iew.wb_sent                      821506514                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     819080726                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 640638640                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1049832937                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     27057833                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 83242296                       # Number of branches executed
+system.cpu.iew.exec_stores                    9121931                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.828800                       # Inst execution rate
+system.cpu.iew.wb_sent                      821550761                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     819129126                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 640649566                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1049893259                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.822793                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.610229                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.822294                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.610204                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        23734474                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1039827                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            910229                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    443141458                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.819237                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.674506                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        23669936                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1040433                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            905908                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    443311497                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.818692                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.674309                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    272292366     61.45%     61.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     11181272      2.52%     63.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3605802      0.81%     64.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     74611152     16.84%     81.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2465682      0.56%     82.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1626284      0.37%     82.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       958421      0.22%     82.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     70995563     16.02%     98.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5404916      1.22%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    272449194     61.46%     61.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     11181690      2.52%     63.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3605884      0.81%     64.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     74618286     16.83%     81.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2464935      0.56%     82.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1628465      0.37%     82.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       954634      0.22%     82.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     70998554     16.02%     98.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5409855      1.22%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    443141458                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            407858109                       # Number of instructions committed
-system.cpu.commit.committedOps              806179275                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    443311497                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            407894468                       # Number of instructions committed
+system.cpu.commit.committedOps              806246903                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       22415696                       # Number of memory references committed
-system.cpu.commit.loads                      13991312                       # Number of loads committed
-system.cpu.commit.membars                      468143                       # Number of memory barriers committed
-system.cpu.commit.branches                   82176077                       # Number of branches committed
+system.cpu.commit.refs                       22423531                       # Number of memory references committed
+system.cpu.commit.loads                      13994611                       # Number of loads committed
+system.cpu.commit.membars                      468283                       # Number of memory barriers committed
+system.cpu.commit.branches                   82184111                       # Number of branches committed
 system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 735014201                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              1155537                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass       171593      0.02%      0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        783328307     97.17%     97.19% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          144946      0.02%     97.20% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv           121298      0.02%     97.22% # Class of committed instruction
+system.cpu.commit.int_insts                 735078702                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1156217                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass       171842      0.02%      0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        783387641     97.16%     97.19% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          145035      0.02%     97.20% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv           121422      0.02%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt             16      0.00%     97.22% # Class of committed instruction
@@ -592,231 +594,230 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        13988731      1.74%     98.96% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        8424384      1.04%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        13992027      1.74%     98.95% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        8428920      1.05%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         806179275                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5404916                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1267572015                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1663421472                       # The number of ROB writes
-system.cpu.timesIdled                          288126                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         2638712                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9810859930                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   407858109                       # Number of Instructions Simulated
-system.cpu.committedOps                     806179275                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.101743                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.101743                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.907653                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.907653                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1091670765                       # number of integer regfile reads
-system.cpu.int_regfile_writes               655627629                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       158                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                 416000684                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                321879904                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               265310647                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 400047                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           1661478                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.997539                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            19061070                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1661990                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.468824                       # Average number of references to valid blocks.
+system.cpu.commit.op_class_0::total         806246903                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               5409855                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1267740043                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1663415417                       # The number of ROB writes
+system.cpu.timesIdled                          288487                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         2630711                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9858723524                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   407894468                       # Number of Instructions Simulated
+system.cpu.committedOps                     806246903                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.102011                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.102011                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.907432                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.907432                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1091775121                       # number of integer regfile reads
+system.cpu.int_regfile_writes               655663425                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       155                       # number of floating regfile reads
+system.cpu.cc_regfile_reads                 416039105                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                321913343                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               265322894                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 400562                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           1662098                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.990156                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            19068760                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1662610                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.469172                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          40620500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.997539                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999995                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999995                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.990156                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999981                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999981                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          225                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          272                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          220                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          275                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88124232                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88124232                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     10914055                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        10914055                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8079827                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8079827                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        64080                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         64080                       # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data      18993882                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         18993882                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     19057962                       # number of overall hits
-system.cpu.dcache.overall_hits::total        19057962                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1815960                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1815960                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       334906                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       334906                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       406730                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       406730                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      2150866                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2150866                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2557596                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2557596                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  27033028000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  27033028000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  13819339247                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  13819339247                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  40852367247                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  40852367247                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  40852367247                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  40852367247                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     12730015                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     12730015                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8414733                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8414733                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       470810                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       470810                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21144748                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21144748                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21615558                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21615558                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.142652                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.142652                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039800                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.039800                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.863894                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.863894                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.101721                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.101721                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.118322                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.118322                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14886.356528                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14886.356528                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41263.337316                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41263.337316                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 18993.450660                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 18993.450660                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15972.955559                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15972.955559                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       469124                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             51580                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.095076                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses          88153475                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88153475                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     10917190                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        10917190                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8084600                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8084600                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        64210                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         64210                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      19001790                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         19001790                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     19066000                       # number of overall hits
+system.cpu.dcache.overall_hits::total        19066000                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1815691                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1815691                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       334621                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       334621                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       406397                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       406397                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      2150312                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2150312                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2556709                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2556709                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  27046737500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  27046737500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  13846171242                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  13846171242                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  40892908742                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  40892908742                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  40892908742                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  40892908742                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     12732881                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12732881                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8419221                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8419221                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       470607                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       470607                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21152102                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21152102                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21622709                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21622709                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.142599                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.142599                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039745                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.039745                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.863559                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.863559                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.101659                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.101659                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.118242                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.118242                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14896.112554                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14896.112554                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41378.667932                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41378.667932                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19017.197849                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19017.197849                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15994.353969                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15994.353969                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       467851                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets           84                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             51332                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.114217                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets           84                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1562865                       # number of writebacks
-system.cpu.dcache.writebacks::total           1562865                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       845003                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       845003                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44547                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        44547                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       889550                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       889550                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       889550                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       889550                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       970957                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       970957                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290359                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       290359                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       403239                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       403239                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1261316                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1261316                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1664555                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1664555                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       602896                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total       602896                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13875                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        13875                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       616771                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total       616771                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  13333994500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  13333994500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12420799750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  12420799750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6058828500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6058828500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25754794250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  25754794250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31813622750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  31813622750                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97793670000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97793670000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2615433000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2615433000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100409103000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 100409103000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076273                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076273                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034506                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034506                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.856479                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.856479                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059652                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.059652                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077007                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.077007                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13732.837294                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13732.837294                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42777.388509                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42777.388509                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15025.403049                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15025.403049                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20418.986400                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20418.986400                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19112.389047                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 19112.389047                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.533133                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.533133                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188499.675676                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188499.675676                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162798.028766                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162798.028766                       # average overall mshr uncacheable latency
+system.cpu.dcache.writebacks::writebacks      1563047                       # number of writebacks
+system.cpu.dcache.writebacks::total           1563047                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       843909                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       843909                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44439                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        44439                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       888348                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       888348                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       888348                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       888348                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       971782                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       971782                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290182                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       290182                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402906                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       402906                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1261964                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1261964                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1664870                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1664870                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       602920                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total       602920                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13934                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        13934                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       616854                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total       616854                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  13356525500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  13356525500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12439701244                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  12439701244                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6060856500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6060856500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25796226744                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  25796226744                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31857083244                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  31857083244                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97797423500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97797423500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2624129500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2624129500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100421553000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 100421553000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076321                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076321                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034467                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034467                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.856141                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.856141                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059661                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.059661                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076996                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.076996                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13744.363962                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13744.363962                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42868.617778                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42868.617778                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15042.854909                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15042.854909                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20441.333306                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20441.333306                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19134.877344                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 19134.877344                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.301831                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.301831                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188325.642314                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188325.642314                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162796.306744                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162796.306744                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements        72618                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse    14.793557                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs       113213                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs        72633                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.558699                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5097094340500                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    14.793557                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.924597                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.924597                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.replacements        73546                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse    14.805379                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs       113695                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs        73561                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.545588                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5097093086500                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    14.805379                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.925336                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.925336                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses       447394                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses       447394                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       113219                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total       113219                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       113219                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total       113219                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       113219                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total       113219                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        73652                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total        73652                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        73652                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total        73652                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        73652                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total        73652                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    910717000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    910717000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    910717000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total    910717000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    910717000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total    910717000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       186871                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       186871                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       186871                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       186871                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       186871                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       186871                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.394133                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.394133                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.394133                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.394133                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.394133                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.394133                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12365.136045                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12365.136045                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12365.136045                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12365.136045                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12365.136045                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12365.136045                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.tag_accesses       451096                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses       451096                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       113711                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total       113711                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       113711                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total       113711                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       113711                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total       113711                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        74558                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total        74558                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        74558                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total        74558                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        74558                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total        74558                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    932190000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    932190000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    932190000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total    932190000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    932190000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total    932190000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       188269                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       188269                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       188269                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       188269                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       188269                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       188269                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.396018                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.396018                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.396018                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.396018                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.396018                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.396018                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12502.883661                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12502.883661                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12502.883661                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12502.883661                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12502.883661                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12502.883661                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -825,180 +826,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks        18815                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total        18815                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        73652                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        73652                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        73652                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total        73652                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        73652                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total        73652                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    837065000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    837065000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    837065000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    837065000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    837065000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    837065000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.394133                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.394133                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.394133                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.394133                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.394133                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.394133                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11365.136045                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11365.136045                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11365.136045                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11365.136045                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11365.136045                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11365.136045                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks        13222                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        13222                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        74558                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        74558                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        74558                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total        74558                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        74558                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total        74558                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    857632000                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    857632000                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    857632000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    857632000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    857632000                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    857632000                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.396018                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.396018                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.396018                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.396018                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.396018                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.396018                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11502.883661                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11502.883661                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11502.883661                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11502.883661                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11502.883661                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11502.883661                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            991040                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.607437                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             8073267                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            991552                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              8.142051                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements            993321                       # number of replacements
+system.cpu.icache.tags.tagsinuse           508.961085                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             8058871                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            993832                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              8.108887                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle      147914027500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.607437                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.995327                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.995327                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          105                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          307                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          100                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          10127588                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         10127588                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      8073267                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         8073267                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       8073267                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          8073267                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      8073267                       # number of overall hits
-system.cpu.icache.overall_hits::total         8073267                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1062411                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1062411                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1062411                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1062411                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1062411                       # number of overall misses
-system.cpu.icache.overall_misses::total       1062411                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14792091486                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14792091486                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14792091486                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14792091486                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14792091486                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14792091486                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9135678                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9135678                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9135678                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9135678                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9135678                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9135678                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.116293                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.116293                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.116293                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.116293                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.116293                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.116293                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13923.134725                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13923.134725                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13923.134725                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13923.134725                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13923.134725                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13923.134725                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         7978                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               382                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    20.884817                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst   508.961085                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.994065                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.994065                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          301                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          113                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          10117194                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         10117194                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      8058871                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         8058871                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       8058871                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          8058871                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      8058871                       # number of overall hits
+system.cpu.icache.overall_hits::total         8058871                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1064420                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1064420                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1064420                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1064420                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1064420                       # number of overall misses
+system.cpu.icache.overall_misses::total       1064420                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  14809433489                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  14809433489                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  14809433489                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  14809433489                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  14809433489                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  14809433489                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9123291                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9123291                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9123291                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9123291                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9123291                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9123291                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.116671                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.116671                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.116671                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.116671                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.116671                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.116671                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13913.148465                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13913.148465                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13913.148465                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13913.148465                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13913.148465                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13913.148465                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         6712                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets           16                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               348                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    19.287356                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets           16                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        70501                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        70501                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        70501                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        70501                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        70501                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        70501                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       991910                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       991910                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       991910                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       991910                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       991910                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       991910                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13114232487                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  13114232487                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13114232487                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  13114232487                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13114232487                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  13114232487                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108575                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108575                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108575                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.108575                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108575                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.108575                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13221.191930                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13221.191930                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13221.191930                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13221.191930                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13221.191930                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13221.191930                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        70517                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        70517                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        70517                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        70517                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        70517                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        70517                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       993903                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       993903                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       993903                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       993903                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       993903                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       993903                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13139309991                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  13139309991                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13139309991                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  13139309991                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13139309991                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  13139309991                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108941                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108941                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108941                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.108941                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108941                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.108941                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13219.911793                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13219.911793                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13219.911793                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13219.911793                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13219.911793                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13219.911793                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements        15565                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     6.022675                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs        26231                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs        15578                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     1.683849                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5102115273500                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.022675                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.376417                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.376417                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           13                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            7                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.812500                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses       101828                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses       101828                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        26240                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        26240                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.replacements        13951                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     6.067078                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs        26495                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs        13966                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     1.897107                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5104644726500                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.067078                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.379192                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.379192                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
+system.cpu.itb_walker_cache.tags.tag_accesses        97508                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        97508                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        26495                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        26495                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        26242                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        26242                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        26242                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        26242                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        16448                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total        16448                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        16448                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total        16448                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        16448                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total        16448                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    193358500                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total    193358500                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    193358500                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total    193358500                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    193358500                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total    193358500                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        42688                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        42688                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        26497                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total        26497                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        26497                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total        26497                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        14838                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total        14838                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        14838                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total        14838                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        14838                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total        14838                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    176788000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total    176788000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    176788000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total    176788000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    176788000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total    176788000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        41333                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        41333                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        42690                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        42690                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        42690                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        42690                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.385307                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.385307                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.385289                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.385289                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.385289                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.385289                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11755.745379                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11755.745379                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11755.745379                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11755.745379                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11755.745379                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11755.745379                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        41335                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        41335                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        41335                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        41335                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.358987                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.358987                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.358969                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.358969                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.358969                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.358969                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11914.543739                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11914.543739                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11914.543739                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11914.543739                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11914.543739                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11914.543739                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -1007,183 +1008,183 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks         3018                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total         3018                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        16448                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        16448                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        16448                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total        16448                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        16448                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total        16448                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    176910500                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    176910500                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    176910500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    176910500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    176910500                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    176910500                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.385307                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.385307                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.385289                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.385289                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.385289                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.385289                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10755.745379                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10755.745379                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10755.745379                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10755.745379                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10755.745379                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10755.745379                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks         1499                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total         1499                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        14838                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        14838                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        14838                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total        14838                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        14838                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total        14838                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    161950000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    161950000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    161950000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    161950000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    161950000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    161950000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.358987                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.358987                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.358969                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.358969                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.358969                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.358969                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10914.543739                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10914.543739                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10914.543739                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10914.543739                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10914.543739                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10914.543739                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           112892                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64819.691770                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4938747                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           176773                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            27.938356                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           112938                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64810.238427                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4946164                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           176935                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            27.954695                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50529.309735                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    20.322898                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.136173                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3138.561208                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11131.361756                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.771016                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000310                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50458.579366                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    20.514879                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.139418                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3172.056588                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11158.948175                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.769937                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000313                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.047891                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.169851                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.989070                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        63881                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          774                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3319                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5177                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54573                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.974747                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         43864381                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        43864381                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      1584698                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1584698                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data          310                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total          310                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       154215                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       154215                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       975190                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       975190                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker        67279                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker        13917                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1337816                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1419012                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        67279                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        13917                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       975190                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1492031                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2548417                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        67279                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        13917                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       975190                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1492031                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2548417                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         1787                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         1787                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       133737                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133737                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16323                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        16323                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker           67                       # number of ReadSharedReq misses
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.048402                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.170272                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.988926                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        63997                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          687                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3372                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5567                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54302                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.976517                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         43925036                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        43925036                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      1577768                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1577768                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data          309                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total          309                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       153927                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       153927                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       977435                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       977435                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker        69221                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker        12891                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1338249                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1420361                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        69221                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker        12891                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       977435                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1492176                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2551723                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        69221                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker        12891                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       977435                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1492176                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2551723                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         1505                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         1505                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       134154                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       134154                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16363                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        16363                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker           70                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker            5                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        35675                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        35747                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           67                       # number of demand (read+write) misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        35783                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        35858                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker           70                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        16323                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       169412                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        185807                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           67                       # number of overall misses
+system.cpu.l2cache.demand_misses::cpu.inst        16363                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       169937                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        186375                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker           70                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        16323                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       169412                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       185807                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     23917000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     23917000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10298204500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  10298204500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1359330500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   1359330500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker      6177500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker       415000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3065419500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   3072012000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      6177500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       415000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1359330500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  13363624000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  14729547000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      6177500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       415000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1359330500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  13363624000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  14729547000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      1584698                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1584698                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2097                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2097                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       287952                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       287952                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       991513                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       991513                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker        67346                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker        13922                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1373491                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1454759                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        67346                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker        13922                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       991513                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1661443                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2734224                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        67346                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker        13922                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       991513                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1661443                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2734224                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.852170                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.852170                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.464442                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.464442                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016463                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016463                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.000995                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker     0.000359                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.025974                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024572                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000995                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000359                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016463                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.101967                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.067956                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000995                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000359                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016463                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.101967                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.067956                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 13383.883604                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 13383.883604                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77003.405939                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77003.405939                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83277.001777                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83277.001777                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 92201.492537                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker        83000                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85926.264891                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85937.617143                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92201.492537                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        83000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83277.001777                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78882.393219                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79273.369679                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92201.492537                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        83000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83277.001777                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78882.393219                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79273.369679                       # average overall miss latency
+system.cpu.l2cache.overall_misses::cpu.inst        16363                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       169937                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       186375                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     23274500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     23274500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10328890000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  10328890000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1358981500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   1358981500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker      6541000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker       429500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3085479000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   3092449500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      6541000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       429500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1358981500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  13414369000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  14780321000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      6541000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       429500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1358981500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  13414369000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  14780321000                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      1577768                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1577768                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1814                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         1814                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       288081                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       288081                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       993798                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       993798                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker        69291                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker        12896                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1374032                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1456219                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker        69291                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker        12896                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       993798                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1662113                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2738098                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker        69291                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker        12896                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       993798                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1662113                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2738098                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.829658                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.829658                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.465682                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.465682                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016465                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016465                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.001010                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker     0.000388                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026042                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024624                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001010                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000388                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016465                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.102242                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.068067                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001010                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000388                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016465                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.102242                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.068067                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15464.784053                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15464.784053                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76992.784412                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76992.784412                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83052.099248                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83052.099248                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 93442.857143                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker        85900                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86227.510270                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86241.550003                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93442.857143                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        85900                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83052.099248                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78937.306178                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 79304.203890                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93442.857143                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        85900                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83052.099248                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78937.306178                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79304.203890                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1192,8 +1193,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       103070                       # number of writebacks
-system.cpu.l2cache.writebacks::total           103070                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       103084                       # number of writebacks
+system.cpu.l2cache.writebacks::total           103084                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            4                       # number of ReadSharedReq MSHR hits
@@ -1204,169 +1205,169 @@ system.cpu.l2cache.demand_mshr_hits::total            6                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data            4                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            6                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           90                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total           90                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1787                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         1787                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133737                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       133737                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16321                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16321                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker           67                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           88                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total           88                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1505                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         1505                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       134154                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       134154                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16361                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16361                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker           70                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker            5                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        35671                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        35743                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           67                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        35779                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        35854                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           70                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        16321                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       169408                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       185801                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           67                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        16361                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       169933                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       186369                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           70                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        16321                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       169408                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       185801                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       602896                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total       602896                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13875                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13875                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       616771                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total       616771                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     37875000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     37875000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8960834500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8960834500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1195971500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1195971500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker      5507500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       365000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2711142000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2717014500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      5507500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       365000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1195971500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11671976500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  12873820500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      5507500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       365000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1195971500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11671976500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  12873820500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  90257461500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  90257461500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2455867500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2455867500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  92713329000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  92713329000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        16361                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       169933                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       186369                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       602920                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total       602920                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13934                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13934                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       616854                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total       616854                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     32097000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     32097000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8987350000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8987350000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1195241000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1195241000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker      5841000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       379500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2728894000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2735114500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      5841000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       379500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1195241000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11716244000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  12917705500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      5841000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       379500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1195241000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11716244000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  12917705500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  90260915500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  90260915500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2463879500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2463879500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  92724795000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  92724795000                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.852170                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.852170                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.464442                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.464442                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016461                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016461                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.000995                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.000359                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.025971                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024570                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000995                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000359                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016461                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101964                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.067954                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000995                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000359                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016461                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101964                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.067954                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21194.739787                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21194.739787                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67003.405939                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67003.405939                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73278.077324                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73278.077324                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 82201.492537                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker        73000                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76004.092961                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76015.289707                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 82201.492537                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        73000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73278.077324                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68898.614587                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69288.219654                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 82201.492537                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        73000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73278.077324                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68898.614587                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69288.219654                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.519035                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.519035                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176999.459459                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176999.459459                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.506314                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.506314                       # average overall mshr uncacheable latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.829658                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.829658                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.465682                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.465682                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016463                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016463                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.001010                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.000388                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026039                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024621                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001010                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000388                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016463                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102239                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.068065                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001010                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000388                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016463                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102239                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.068065                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21326.910299                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21326.910299                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66992.784412                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66992.784412                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73054.275411                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73054.275411                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 83442.857143                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker        75900                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76270.829257                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76284.779941                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83442.857143                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        75900                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73054.275411                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68946.255289                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69312.522469                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83442.857143                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        75900                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73054.275411                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68946.255289                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69312.522469                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.288562                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.288562                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176824.996412                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176824.996412                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150318.867998                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150318.867998                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq         602896                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3059319                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         13875                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        13875                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1734439                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      1113474                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2547                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2547                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       287963                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       287963                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       991910                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1465068                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::MessageReq         1642                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           22                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         602920                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3061153                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         13934                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        13934                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1727529                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      1124352                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2232                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2232                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       288090                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       288090                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       993903                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1464872                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::MessageReq         1650                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           12                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        46720                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2973341                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6222105                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        35861                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       172954                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           9404261                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     63456832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    208155201                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      1084160                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5514304                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          278210497                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      220375                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      6313792                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        3.033219                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.179209                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2979851                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6223737                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        32716                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       177236                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           9413540                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     63603072                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    208211079                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       921280                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5280832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          278016263                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      218468                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      6317764                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        3.033210                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.179185                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            6104051     96.68%     96.68% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4             209741      3.32%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            6107951     96.68%     96.68% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4             209813      3.32%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        6313792                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4643672976                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        6317764                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4638715490                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       564000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       577500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1489388443                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1492354491                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3104272690                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3105124685                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      24683477                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      22263487                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     110523908                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     111892387                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq               222096                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              222096                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57708                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              57708                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1642                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1642                       # Transaction distribution
+system.iobus.trans_dist::ReadReq               222126                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              222126                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57753                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              57753                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1650                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1650                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11042                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
@@ -1382,15 +1383,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       464350                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95258                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95258                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3284                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3284                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  562892                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       464488                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95270                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95270                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3300                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3300                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  563058                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6660                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
@@ -1406,19 +1407,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       238452                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027816                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027816                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6568                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6568                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  3272836                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              3914184                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total       238530                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027864                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027864                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6600                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6600                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  3272994                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              3933000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              8775000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              8889000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -1448,54 +1449,54 @@ system.iobus.reqLayer17.occupancy                9000                       # La
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy           242657095                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy           242643106                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           453362000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           453455000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            50170000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            50182000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1642000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1650000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47574                       # number of replacements
-system.iocache.tags.tagsinuse                0.103760                       # Cycle average of tags in use
+system.iocache.tags.replacements                47580                       # number of replacements
+system.iocache.tags.tagsinuse                0.177808                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47590                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47596                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         4993210499000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.103760                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006485                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.006485                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         4993210705000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.177808                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.011113                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.011113                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428661                       # Number of tag accesses
-system.iocache.tags.data_accesses              428661                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          909                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              909                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               428715                       # Number of tag accesses
+system.iocache.tags.data_accesses              428715                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          915                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              915                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          909                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               909                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          909                       # number of overall misses
-system.iocache.overall_misses::total              909                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    141558677                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    141558677                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   5512975418                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   5512975418                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    141558677                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    141558677                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    141558677                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    141558677                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          909                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            909                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide          915                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               915                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          915                       # number of overall misses
+system.iocache.overall_misses::total              915                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    142818702                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    142818702                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   5513453404                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   5513453404                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    142818702                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    142818702                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    142818702                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    142818702                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          915                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            915                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          909                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             909                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          909                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            909                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide          915                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             915                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          915                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            915                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
@@ -1504,40 +1505,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155730.117712                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 155730.117712                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118000.330009                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118000.330009                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 155730.117712                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 155730.117712                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 155730.117712                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 155730.117712                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           548                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156086.013115                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 156086.013115                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118010.560873                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118010.560873                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156086.013115                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 156086.013115                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156086.013115                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 156086.013115                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           218                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   46                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   18                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    11.913043                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    12.111111                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          909                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          909                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          915                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          915                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        46720                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          909                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          909                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          909                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          909                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     96108677                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     96108677                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3176975418                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3176975418                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     96108677                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     96108677                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     96108677                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     96108677                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          915                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          915                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          915                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          915                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     97068702                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     97068702                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3177453404                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3177453404                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     97068702                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     97068702                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     97068702                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     97068702                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1546,81 +1547,81 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105730.117712                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 105730.117712                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68000.330009                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68000.330009                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105730.117712                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 105730.117712                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105730.117712                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 105730.117712                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106086.013115                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 106086.013115                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68010.560873                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68010.560873                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 106086.013115                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 106086.013115                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 106086.013115                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 106086.013115                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              602896                       # Transaction distribution
-system.membus.trans_dist::ReadResp             655847                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13875                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13875                       # Transaction distribution
-system.membus.trans_dist::Writeback            149737                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            10183                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2524                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            2074                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            133454                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           133450                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         52973                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1642                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1642                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           22                       # Transaction distribution
+system.membus.trans_dist::ReadReq              602920                       # Transaction distribution
+system.membus.trans_dist::ReadResp             656038                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13934                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13934                       # Transaction distribution
+system.membus.trans_dist::Writeback            149751                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            10203                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2209                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1791                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            133869                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           133868                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         53130                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1650                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1650                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           12                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3284                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3284                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       464350                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       769192                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       487788                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           44                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1721374                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141823                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       141823                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1866481                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       238452                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1538381                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18425216                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20202049                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3300                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3300                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       464488                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       769220                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       488383                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           24                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1722115                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141817                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       141817                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1867232                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6600                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total         6600                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       238530                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1538437                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18462656                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20239623                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3015040                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      3015040                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                23223657                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             1607                       # Total snoops (count)
-system.membus.snoop_fanout::samples           1014551                       # Request fanout histogram
-system.membus.snoop_fanout::mean             1.001618                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.040197                       # Request fanout histogram
+system.membus.pkt_size::total                23261263                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             1586                       # Total snoops (count)
+system.membus.snoop_fanout::samples           1014957                       # Request fanout histogram
+system.membus.snoop_fanout::mean             1.001626                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.040287                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 1012909     99.84%     99.84% # Request fanout histogram
-system.membus.snoop_fanout::2                    1642      0.16%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 1013307     99.84%     99.84% # Request fanout histogram
+system.membus.snoop_fanout::2                    1650      0.16%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
-system.membus.snoop_fanout::total             1014551                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           354940000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             1014957                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           355040500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           388594500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           388549500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3284000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3300000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1018302522                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1018755770                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy               27500                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy               14000                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1642000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1650000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2206598693                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2209187226                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           86075861                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           86115345                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           29                       # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
 system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
index 9aafe0fe834fa6f60b65d79139140c18b83e52ce..ba1f8e728999f0b80bbd601c195b7c3f7336e5d4 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  5.141168                       # Nu
 sim_ticks                                5141168437500                       # Number of ticks simulated
 final_tick                               5141168437500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 561125                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1115525                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            11816760555                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 973408                       # Number of bytes of host memory used
-host_seconds                                   435.07                       # Real time elapsed on the host
+host_inst_rate                                 195369                       # Simulator instruction rate (inst/s)
+host_op_rate                                   388397                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4114294038                       # Simulator tick rate (ticks/s)
+host_mem_usage                                1021404                       # Number of bytes of host memory used
+host_seconds                                  1249.59                       # Real time elapsed on the host
 sim_insts                                   244131065                       # Number of instructions simulated
 sim_ops                                     485336254                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -133,9 +133,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  81462                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     89320                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                     89319                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                      4643                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       843                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       844                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                       184                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        44                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                        34                       # What read queue length does an incoming req see
@@ -189,10 +189,10 @@ system.physmem.wrQLenPdf::20                     4383                       # Wh
 system.physmem.wrQLenPdf::21                     4398                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::22                     5113                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::23                     5221                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6010                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5226                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4638                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5387                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5227                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4640                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::28                     4893                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::29                     4936                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                     4337                       # What write queue length does an incoming req see
@@ -229,20 +229,20 @@ system.physmem.wrQLenPdf::60                        9                       # Wh
 system.physmem.wrQLenPdf::61                        6                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        4                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        3                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        41437                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      273.022082                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     164.972231                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     298.458037                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          16767     40.46%     40.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10137     24.46%     64.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4304     10.39%     75.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2528      6.10%     81.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples        41433                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      273.048440                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     164.990010                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     298.466349                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          16764     40.46%     40.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10136     24.46%     64.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4303     10.39%     75.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2529      6.10%     81.41% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::512-639         1659      4.00%     85.42% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::640-767         1139      2.75%     88.17% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::768-895          786      1.90%     90.06% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::896-1023          657      1.59%     91.65% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151         3460      8.35%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          41437                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          41433                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          4254                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::mean        22.404325                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::stdev      181.210886                       # Reads before turning the bus around for writes
@@ -283,12 +283,12 @@ system.physmem.wrPerTurnAround::132-135             1      0.02%     99.95% # Wr
 system.physmem.wrPerTurnAround::156-159             1      0.02%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::164-167             1      0.02%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            4254                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1082395298                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2869457798                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                     1082376548                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2869439048                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                    476550000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11356.58                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       11356.38                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30106.58                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  30106.38                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.19                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.01                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.19                       # Average system read bandwidth in MiByte/s
@@ -299,21 +299,21 @@ system.physmem.busUtilRead                       0.01                       # Da
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         9.18                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      76601                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     58731                       # Number of row buffer hits during writes
+system.physmem.readRowHits                      76603                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     58733                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   80.37                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  72.10                       # Row buffer hit rate for writes
 system.physmem.avgGap                     29060364.94                       # Average gap between requests
 system.physmem.pageHitRate                      76.56                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  152477640                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   82953750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.actEnergy                  152447400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   82937250                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                 356538000                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                270228960                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           250406807040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            95253378300                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           2241273732750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             2587796116440                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.867379                       # Core power per rank (mW)
+system.physmem_0.actBackEnergy            95253368040                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           2241273741750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             2587796068440                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.867367                       # Core power per rank (mW)
 system.physmem_0.memoryStateTime::IDLE   3687953773966                       # Time in different power states
 system.physmem_0.memoryStateTime::REF    128019840000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
@@ -324,14 +324,14 @@ system.physmem_1.preEnergy                   87503625                       # En
 system.physmem_1.readEnergy                 386872200                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                257631840                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           250406807040                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            95644179990                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           2237947569750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             2584891350525                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.974891                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   3687410747240                       # Time in different power states
+system.physmem_1.actBackEnergy            95642577720                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           2237948975250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             2584891153755                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.974840                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   3687413088990                       # Time in different power states
 system.physmem_1.memoryStateTime::REF    128019840000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     18840857760                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     18838516010                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
@@ -459,17 +459,17 @@ system.cpu0.dcache.overall_misses::cpu1.data       297649
 system.cpu0.dcache.overall_misses::cpu2.data      1159923                       # number of overall misses
 system.cpu0.dcache.overall_misses::total      2062841                       # number of overall misses
 system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2308605500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  12073568500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  14382174000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  12073522500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  14382128000                       # number of ReadReq miss cycles
 system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2733996493                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   4762186878                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   7496183371                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   4762162878                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   7496159371                       # number of WriteReq miss cycles
 system.cpu0.dcache.demand_miss_latency::cpu1.data   5042601993                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  16835755378                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  21878357371                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  16835685378                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  21878287371                       # number of demand (read+write) miss cycles
 system.cpu0.dcache.overall_miss_latency::cpu1.data   5042601993                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  16835755378                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  21878357371                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  16835685378                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  21878287371                       # number of overall miss cycles
 system.cpu0.dcache.ReadReq_accesses::cpu0.data      5034107                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::cpu1.data      2741577                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::cpu2.data      5078638                       # number of ReadReq accesses(hits+misses)
@@ -511,17 +511,17 @@ system.cpu0.dcache.overall_miss_rate::cpu1.data     0.063379
 system.cpu0.dcache.overall_miss_rate::cpu2.data     0.136727                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::total     0.094912                       # miss rate for overall accesses
 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13908.518842                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14643.077097                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10802.472326                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14643.021307                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10802.437775                       # average ReadReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40378.031207                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 34712.346949                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 23035.198406                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 34712.172010                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 23035.124656                       # average WriteReq miss latency
 system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21577.705954                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17505.989700                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 13205.181172                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17505.916913                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 13205.138922                       # average overall miss latency
 system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16941.437710                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14514.545688                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 10605.934908                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14514.485339                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 10605.900974                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs       198021                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs            23048                       # number of cycles access was blocked
@@ -569,20 +569,20 @@ system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data       189368
 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data       209170                       # number of overall MSHR uncacheable misses
 system.cpu0.dcache.overall_mshr_uncacheable_misses::total       398538                       # number of overall MSHR uncacheable misses
 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2142200000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5924742500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   8066942500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5924733500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   8066933500                       # number of ReadReq MSHR miss cycles
 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2581607993                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   4076188379                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6657796372                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   4076164379                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6657772372                       # number of WriteReq MSHR miss cycles
 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    949074500                       # number of SoftPFReq MSHR miss cycles
 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2819608000                       # number of SoftPFReq MSHR miss cycles
 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3768682500                       # number of SoftPFReq MSHR miss cycles
 system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4723807993                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  10000930879                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  14724738872                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  10000897879                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  14724705872                       # number of demand (read+write) MSHR miss cycles
 system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   5672882493                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  12820538879                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  18493421372                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  12820505879                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  18493388372                       # number of overall MSHR miss cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30610037000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33210281500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63820318500                       # number of ReadReq MSHR uncacheable cycles
@@ -608,20 +608,20 @@ system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.063034
 system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.087132                       # mshr miss rate for overall accesses
 system.cpu0.dcache.overall_mshr_miss_rate::total     0.047631                       # mshr miss rate for overall accesses
 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12909.952150                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13489.666580                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13330.704465                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13489.646089                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13330.689592                       # average ReadReq mshr miss latency
 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39030.706091                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 38753.300239                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38860.396974                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 38753.072065                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38860.256890                       # average WriteReq mshr miss latency
 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14839.955280                       # average SoftPFReq mshr miss latency
 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14474.596631                       # average SoftPFReq mshr miss latency
 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14564.900232                       # average SoftPFReq mshr miss latency
 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20354.485766                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18370.927552                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18963.790909                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18370.866933                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18963.748409                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19163.136607                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17344.131083                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17864.294512                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17344.086440                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17864.262635                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164538.245286                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 162011.647080                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163213.720165                       # average ReadReq mshr uncacheable latency
@@ -632,11 +632,11 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164769.126780
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162777.138213                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163723.644922                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           878678                       # number of replacements
+system.cpu0.icache.tags.replacements           878679                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          510.838296                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          128369667                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           879190                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           146.009016                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.total_refs          128369666                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           879191                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           146.008849                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle     149037485500                       # Cycle when the warmup percentage was hit.
 system.cpu0.icache.tags.occ_blocks::cpu0.inst   260.884696                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_blocks::cpu1.inst   143.250304                       # Average occupied blocks per requestor
@@ -651,41 +651,41 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1          148
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          300                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        130155693                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       130155693                       # Number of data accesses
+system.cpu0.icache.tags.tag_accesses        130155694                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       130155694                       # Number of data accesses
 system.cpu0.icache.ReadReq_hits::cpu0.inst     85680859                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::cpu1.inst     39485533                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      3203275                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      128369667                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      3203274                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      128369666                       # number of ReadReq hits
 system.cpu0.icache.demand_hits::cpu0.inst     85680859                       # number of demand (read+write) hits
 system.cpu0.icache.demand_hits::cpu1.inst     39485533                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      3203275                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       128369667                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      3203274                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       128369666                       # number of demand (read+write) hits
 system.cpu0.icache.overall_hits::cpu0.inst     85680859                       # number of overall hits
 system.cpu0.icache.overall_hits::cpu1.inst     39485533                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      3203275                       # number of overall hits
-system.cpu0.icache.overall_hits::total      128369667                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      3203274                       # number of overall hits
+system.cpu0.icache.overall_hits::total      128369666                       # number of overall hits
 system.cpu0.icache.ReadReq_misses::cpu0.inst       290083                       # number of ReadReq misses
 system.cpu0.icache.ReadReq_misses::cpu1.inst       179832                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       436910                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       906825                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       436911                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       906826                       # number of ReadReq misses
 system.cpu0.icache.demand_misses::cpu0.inst       290083                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::cpu1.inst       179832                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       436910                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        906825                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       436911                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        906826                       # number of demand (read+write) misses
 system.cpu0.icache.overall_misses::cpu0.inst       290083                       # number of overall misses
 system.cpu0.icache.overall_misses::cpu1.inst       179832                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       436910                       # number of overall misses
-system.cpu0.icache.overall_misses::total       906825                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       436911                       # number of overall misses
+system.cpu0.icache.overall_misses::total       906826                       # number of overall misses
 system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2559612500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   6034776488                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   8594388988                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   6034803488                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   8594415988                       # number of ReadReq miss cycles
 system.cpu0.icache.demand_miss_latency::cpu1.inst   2559612500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   6034776488                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   8594388988                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   6034803488                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   8594415988                       # number of demand (read+write) miss cycles
 system.cpu0.icache.overall_miss_latency::cpu1.inst   2559612500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   6034776488                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   8594388988                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   6034803488                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   8594415988                       # number of overall miss cycles
 system.cpu0.icache.ReadReq_accesses::cpu0.inst     85970942                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.ReadReq_accesses::cpu1.inst     39665365                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.ReadReq_accesses::cpu2.inst      3640185                       # number of ReadReq accesses(hits+misses)
@@ -711,14 +711,14 @@ system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004534
 system.cpu0.icache.overall_miss_rate::cpu2.inst     0.120024                       # miss rate for overall accesses
 system.cpu0.icache.overall_miss_rate::total     0.007015                       # miss rate for overall accesses
 system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14233.353908                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13812.401840                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9477.450432                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13812.432024                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9477.469755                       # average ReadReq miss latency
 system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14233.353908                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13812.401840                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9477.450432                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13812.432024                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9477.469755                       # average overall miss latency
 system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14233.353908                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13812.401840                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9477.450432                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13812.432024                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9477.469755                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs         5682                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs              315                       # number of cycles access was blocked
@@ -734,41 +734,41 @@ system.cpu0.icache.demand_mshr_hits::total        27624                       #
 system.cpu0.icache.overall_mshr_hits::cpu2.inst        27624                       # number of overall MSHR hits
 system.cpu0.icache.overall_mshr_hits::total        27624                       # number of overall MSHR hits
 system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       179832                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       409286                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       589118                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       409287                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       589119                       # number of ReadReq MSHR misses
 system.cpu0.icache.demand_mshr_misses::cpu1.inst       179832                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       409286                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       589118                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       409287                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       589119                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.overall_mshr_misses::cpu1.inst       179832                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       409286                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       589118                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       409287                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       589119                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2379780500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   5367725488                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   7747505988                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   5367751488                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   7747531988                       # number of ReadReq MSHR miss cycles
 system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2379780500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   5367725488                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   7747505988                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   5367751488                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   7747531988                       # number of demand (read+write) MSHR miss cycles
 system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2379780500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   5367725488                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   7747505988                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   5367751488                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   7747531988                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004534                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.112435                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.112436                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004557                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004534                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.112435                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.112436                       # mshr miss rate for demand accesses
 system.cpu0.icache.demand_mshr_miss_rate::total     0.004557                       # mshr miss rate for demand accesses
 system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004534                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.112435                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.112436                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_miss_rate::total     0.004557                       # mshr miss rate for overall accesses
 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13233.353908                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13114.852421                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13151.025750                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13114.883903                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13151.047561                       # average ReadReq mshr miss latency
 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13233.353908                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13114.852421                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13151.025750                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13114.883903                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13151.047561                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13233.353908                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13114.852421                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13151.025750                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13114.883903                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13151.047561                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.numCycles                      2607160707                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
@@ -832,23 +832,23 @@ system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Cl
 system.cpu1.op_class::total                  69696027                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups               29601975                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         29601975                       # Number of conditional branches predicted
+system.cpu2.branchPred.lookups               29601973                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         29601973                       # Number of conditional branches predicted
 system.cpu2.branchPred.condIncorrect           343203                       # Number of conditional branches incorrect
 system.cpu2.branchPred.BTBLookups            26791839                       # Number of BTB lookups
 system.cpu2.branchPred.BTBHits               26086008                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu2.branchPred.BTBHitPct            97.365500                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 612616                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.usedRAS                 612615                       # Number of times the RAS was used to get a target.
 system.cpu2.branchPred.RASInCorrect             69103                       # Number of incorrect RAS predictions.
 system.cpu2.numCycles                       155854675                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles          11239571                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                     145909604                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   29601975                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          26698624                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                    143043306                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.icacheStallCycles          11239570                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                     145909603                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   29601973                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          26698623                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                    143043279                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu2.fetch.SquashCycles                 717621                       # Number of cycles fetch has spent squashing
 system.cpu2.fetch.TlbCycles                    104333                       # Number of cycles fetch has spent waiting for tlb
 system.cpu2.fetch.MiscStallCycles                8734                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
@@ -857,13 +857,13 @@ system.cpu2.fetch.PendingTrapStallCycles        59780                       # Nu
 system.cpu2.fetch.PendingQuiesceStallCycles           15                       # Number of stall cycles due to pending quiesce instructions
 system.cpu2.fetch.IcacheWaitRetryStallCycles          573                       # Number of stall cycles due to full MSHR
 system.cpu2.fetch.CacheLines                  3640195                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               178300                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.IcacheSquashes               178301                       # Number of outstanding Icache misses that were squashed
 system.cpu2.fetch.ItlbSquashes                   3755                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples         154824000                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::samples         154823972                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::mean             1.854554                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::stdev            3.033337                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                98922679     63.89%     63.89% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                98922650     63.89%     63.89% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::1                  904691      0.58%     64.48% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::2                23796776     15.37%     79.85% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::3                  606779      0.39%     80.24% # Number of instructions fetched each cycle (Total)
@@ -871,36 +871,36 @@ system.cpu2.fetch.rateDist::4                  848220      0.55%     80.79% # Nu
 system.cpu2.fetch.rateDist::5                  866864      0.56%     81.35% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::6                  584872      0.38%     81.73% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::7                  770506      0.50%     82.22% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                27522613     17.78%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                27522614     17.78%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total           154824000                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::total           154823972                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.branchRate                 0.189933                       # Number of branch fetches per cycle
 system.cpu2.fetch.rate                       0.936190                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                10345116                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             94152744                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 23674011                       # Number of cycles decode is running
+system.cpu2.decode.IdleCycles                10345115                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             94152716                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 23674012                       # Number of cycles decode is running
 system.cpu2.decode.UnblockCycles              5064791                       # Number of cycles decode is unblocking
 system.cpu2.decode.SquashCycles                359462                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts             284127557                       # Number of instructions handled by decode
+system.cpu2.decode.DecodedInsts             284127567                       # Number of instructions handled by decode
 system.cpu2.rename.SquashCycles                359462                       # Number of cycles rename is squashing
 system.cpu2.rename.IdleCycles                12498058                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles               76923253                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       4647068                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.BlockCycles               76923279                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       4647064                       # count of cycles rename stalled for serializing inst
 system.cpu2.rename.RunCycles                 26307426                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles             12860925                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts             282811274                       # Number of instructions processed by rename
+system.cpu2.rename.UnblockCycles             12860875                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts             282811276                       # Number of instructions processed by rename
 system.cpu2.rename.ROBFullEvents               202798                       # Number of times rename has blocked due to ROB full
 system.cpu2.rename.IQFullEvents               5895071                       # Number of times rename has blocked due to IQ full
 system.cpu2.rename.LQFullEvents                 49763                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               4758021                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands          337796411                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            617680830                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       379222273                       # Number of integer rename lookups
+system.cpu2.rename.SQFullEvents               4757971                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands          337796416                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            617680837                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       379222279                       # Number of integer rename lookups
 system.cpu2.rename.fp_rename_lookups              178                       # Number of floating rename lookups
 system.cpu2.rename.CommittedMaps            324911571                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                12884840                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.UndoneMaps                12884845                       # Number of HB maps that are undone due to squashing
 system.cpu2.rename.serializingInsts            166150                       # count of serializing insts renamed
 system.cpu2.rename.tempSerializingInsts        167782                       # count of temporary serializing insts renamed
 system.cpu2.rename.skidInsts                 24657180                       # count of insts added to the skid buffer
@@ -908,18 +908,18 @@ system.cpu2.memDep0.insertedLoads             6871363                       # Nu
 system.cpu2.memDep0.insertedStores            3845087                       # Number of stores inserted to the mem dependence unit.
 system.cpu2.memDep0.conflictingLoads           401055                       # Number of conflicting loads.
 system.cpu2.memDep0.conflictingStores          322271                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                 280748482                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqInstsAdded                 280748481                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu2.iq.iqNonSpecInstsAdded             429304                       # Number of non-speculative instructions added to the IQ
 system.cpu2.iq.iqInstsIssued                278478009                       # Number of instructions issued
 system.cpu2.iq.iqSquashedInstsIssued           108269                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        9486121                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     14384380                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedInstsExamined        9486120                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     14384377                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu2.iq.iqSquashedNonSpecRemoved         66849                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples    154824000                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::samples    154823972                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::mean        1.798675                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::stdev       2.397594                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           91620665     59.18%     59.18% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           91620637     59.18%     59.18% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::1            5352321      3.46%     62.63% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::2            3836914      2.48%     65.11% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::3            3858930      2.49%     67.61% # Number of insts issued each cycle
@@ -931,7 +931,7 @@ system.cpu2.iq.issued_per_cycle::8             223159      0.14%    100.00% # Nu
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total      154824000                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total      154823972                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IntAlu                1768977     86.18%     86.18% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IntMult                     0      0.00%     86.18% # attempts to use FU when none available
@@ -1004,8 +1004,8 @@ system.cpu2.iq.FU_type_0::total             278478009                       # Ty
 system.cpu2.iq.rate                          1.786780                       # Inst issue rate
 system.cpu2.iq.fu_busy_cnt                    2052604                       # FU busy when requested
 system.cpu2.iq.fu_busy_rate                  0.007371                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         713940635                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes        290668152                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_reads         713940607                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes        290668150                       # Number of integer instruction queue writes
 system.cpu2.iq.int_inst_queue_wakeup_accesses    276821518                       # Number of integer instruction queue wakeup accesses
 system.cpu2.iq.fp_inst_queue_reads                256                       # Number of floating instruction queue reads
 system.cpu2.iq.fp_inst_queue_writes               236                       # Number of floating instruction queue writes
@@ -1024,15 +1024,15 @@ system.cpu2.iew.lsq.thread0.rescheduledLoads       750358
 system.cpu2.iew.lsq.thread0.cacheBlocked        29268                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
 system.cpu2.iew.iewSquashCycles                359462                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles               70735172                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles              3134720                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts          281177786                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewBlockCycles               70735218                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles              3134704                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts          281177785                       # Number of instructions dispatched to IQ
 system.cpu2.iew.iewDispSquashedInsts            44449                       # Number of squashed instructions skipped by dispatch
 system.cpu2.iew.iewDispLoadInsts              6871363                       # Number of dispatched load instructions
 system.cpu2.iew.iewDispStoreInsts             3845087                       # Number of dispatched store instructions
 system.cpu2.iew.iewDispNonSpecInsts            251829                       # Number of dispatched non-speculative instructions
 system.cpu2.iew.iewIQFullEvents                166997                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents              2638315                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents              2638299                       # Number of times the LSQ has become full, causing a stall
 system.cpu2.iew.memOrderViolationEvents          5109                       # Number of memory order violations
 system.cpu2.iew.predictedTakenIncorrect        196795                       # Number of branches that were predicted taken incorrectly
 system.cpu2.iew.predictedNotTakenIncorrect       202269                       # Number of branches that were predicted not taken incorrectly
@@ -1054,14 +1054,14 @@ system.cpu2.iew.wb_penalized                        0                       # nu
 system.cpu2.iew.wb_rate                      1.776152                       # insts written-back per cycle
 system.cpu2.iew.wb_fanout                    0.609742                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        9482299                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitSquashedInsts        9482298                       # The number of squashed insts skipped by commit
 system.cpu2.commit.commitNonSpecStalls         362455                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu2.commit.branchMispredicts           346445                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples    153408377                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.771035                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::samples    153408349                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.771036                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::stdev     2.652208                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     95336138     62.15%     62.15% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     95336110     62.15%     62.15% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::1      4415580      2.88%     65.02% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::2      1307869      0.85%     65.88% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::3     24753928     16.14%     82.01% # Number of insts commited each cycle
@@ -1073,7 +1073,7 @@ system.cpu2.commit.committed_per_cycle::8      2113838      1.38%    100.00% # N
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total    153408377                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::total    153408349                       # Number of insts commited each cycle
 system.cpu2.commit.committedInsts           137757751                       # Number of instructions committed
 system.cpu2.commit.committedOps             271691665                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
@@ -1120,10 +1120,10 @@ system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Cl
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::total        271691665                       # Class of committed instruction
 system.cpu2.commit.bw_lim_events              2113838                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                   432438077                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  563770770                       # The number of ROB writes
+system.cpu2.rob.rob_reads                   432438048                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  563770768                       # The number of ROB writes
 system.cpu2.timesIdled                         121162                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        1030675                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.idleCycles                        1030703                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu2.quiesceCycles                  4911308393                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
 system.cpu2.committedInsts                  137757751                       # Number of Instructions Simulated
 system.cpu2.committedOps                    271691665                       # Number of Ops (including micro ops) Simulated
@@ -1330,11 +1330,11 @@ system.iocache.overall_avg_mshr_miss_latency::total 116467.334214
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                   105183                       # number of replacements
 system.l2c.tags.tagsinuse                64828.721241                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4684113                       # Total number of references to valid blocks.
+system.l2c.tags.total_refs                    4684115                       # Total number of references to valid blocks.
 system.l2c.tags.sampled_refs                   169423                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    27.647445                       # Average number of references to valid blocks.
+system.l2c.tags.avg_refs                    27.647456                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   50898.132317                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks   50898.132312                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.126487                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.inst     1607.202570                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.data     5199.796885                       # Average occupied blocks per requestor
@@ -1342,7 +1342,7 @@ system.l2c.tags.occ_blocks::cpu1.inst      251.414397                       # Av
 system.l2c.tags.occ_blocks::cpu1.data     1573.306131                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu2.dtb.walker     6.399418                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu2.itb.walker     0.004770                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     1229.783271                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     1229.783276                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu2.data     4062.554995                       # Average occupied blocks per requestor
 system.l2c.tags.occ_percent::writebacks      0.776644                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
@@ -1362,8 +1362,8 @@ system.l2c.tags.age_task_id_blocks_1024::2         3044                       #
 system.l2c.tags.age_task_id_blocks_1024::3         6984                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::4        54074                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.980225                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 41790314                       # Number of tag accesses
-system.l2c.tags.data_accesses                41790314                       # Number of data accesses
+system.l2c.tags.tag_accesses                 41790330                       # Number of tag accesses
+system.l2c.tags.data_accesses                41790330                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.dtb.walker        18694                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.itb.walker        10376                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.dtb.walker        14927                       # number of ReadReq hits
@@ -1385,8 +1385,8 @@ system.l2c.ReadExReq_hits::cpu2.data            63793                       # nu
 system.l2c.ReadExReq_hits::total               159309                       # number of ReadExReq hits
 system.l2c.ReadCleanReq_hits::cpu0.inst        284171                       # number of ReadCleanReq hits
 system.l2c.ReadCleanReq_hits::cpu1.inst        176684                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst        403286                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total            864141                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst        403287                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total            864142                       # number of ReadCleanReq hits
 system.l2c.ReadSharedReq_hits::cpu0.data       469690                       # number of ReadSharedReq hits
 system.l2c.ReadSharedReq_hits::cpu1.data       225324                       # number of ReadSharedReq hits
 system.l2c.ReadSharedReq_hits::cpu2.data       620313                       # number of ReadSharedReq hits
@@ -1401,9 +1401,9 @@ system.l2c.demand_hits::cpu1.inst              176684                       # nu
 system.l2c.demand_hits::cpu1.data              263579                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu2.dtb.walker         63394                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu2.itb.walker         13067                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              403286                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst              403287                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu2.data              684106                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2467689                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2467690                       # number of demand (read+write) hits
 system.l2c.overall_hits::cpu0.dtb.walker        18694                       # number of overall hits
 system.l2c.overall_hits::cpu0.itb.walker        10378                       # number of overall hits
 system.l2c.overall_hits::cpu0.inst             284171                       # number of overall hits
@@ -1414,9 +1414,9 @@ system.l2c.overall_hits::cpu1.inst             176684                       # nu
 system.l2c.overall_hits::cpu1.data             263579                       # number of overall hits
 system.l2c.overall_hits::cpu2.dtb.walker        63394                       # number of overall hits
 system.l2c.overall_hits::cpu2.itb.walker        13067                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             403286                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst             403287                       # number of overall hits
 system.l2c.overall_hits::cpu2.data             684106                       # number of overall hits
-system.l2c.overall_hits::total                2467689                       # number of overall hits
+system.l2c.overall_hits::total                2467690                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.itb.walker            5                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu2.dtb.walker           37                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu2.itb.walker            1                       # number of ReadReq misses
@@ -1464,28 +1464,28 @@ system.l2c.UpgradeReq_miss_latency::cpu1.data      6342500
 system.l2c.UpgradeReq_miss_latency::cpu2.data      7566000                       # number of UpgradeReq miss cycles
 system.l2c.UpgradeReq_miss_latency::total     13908500                       # number of UpgradeReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu1.data   2068321500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   3225795000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   5294116500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data   3225771000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   5294092500                       # number of ReadExReq miss cycles
 system.l2c.ReadCleanReq_miss_latency::cpu1.inst    254232000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst    507297500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total    761529500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu2.inst    507311500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total    761543500                       # number of ReadCleanReq miss cycles
 system.l2c.ReadSharedReq_miss_latency::cpu1.data    380479000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2.data   1184085000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total   1564564000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu2.data   1184076000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total   1564555000                       # number of ReadSharedReq miss cycles
 system.l2c.demand_miss_latency::cpu1.inst    254232000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu1.data   2448800500                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu2.dtb.walker      3871500                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu2.itb.walker        83000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst    507297500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   4409880000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      7624164500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst    507311500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data   4409847000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      7624145500                       # number of demand (read+write) miss cycles
 system.l2c.overall_miss_latency::cpu1.inst    254232000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.data   2448800500                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu2.dtb.walker      3871500                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu2.itb.walker        83000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst    507297500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data   4409880000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     7624164500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst    507311500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data   4409847000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     7624145500                       # number of overall miss cycles
 system.l2c.ReadReq_accesses::cpu0.dtb.walker        18694                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu0.itb.walker        10381                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.dtb.walker        14927                       # number of ReadReq accesses(hits+misses)
@@ -1507,8 +1507,8 @@ system.l2c.ReadExReq_accesses::cpu2.data       104536                       # nu
 system.l2c.ReadExReq_accesses::total           290245                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadCleanReq_accesses::cpu0.inst       290070                       # number of ReadCleanReq accesses(hits+misses)
 system.l2c.ReadCleanReq_accesses::cpu1.inst       179832                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst       409276                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total        879178                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst       409277                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total        879179                       # number of ReadCleanReq accesses(hits+misses)
 system.l2c.ReadSharedReq_accesses::cpu0.data       484746                       # number of ReadSharedReq accesses(hits+misses)
 system.l2c.ReadSharedReq_accesses::cpu1.data       229888                       # number of ReadSharedReq accesses(hits+misses)
 system.l2c.ReadSharedReq_accesses::cpu2.data       633950                       # number of ReadSharedReq accesses(hits+misses)
@@ -1523,9 +1523,9 @@ system.l2c.demand_accesses::cpu1.inst          179832                       # nu
 system.l2c.demand_accesses::cpu1.data          295642                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu2.dtb.walker        63431                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu2.itb.walker        13068                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst          409276                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst          409277                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu2.data          738486                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2646962                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2646963                       # number of demand (read+write) accesses
 system.l2c.overall_accesses::cpu0.dtb.walker        18694                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu0.itb.walker        10383                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu0.inst         290070                       # number of overall (read+write) accesses
@@ -1536,9 +1536,9 @@ system.l2c.overall_accesses::cpu1.inst         179832                       # nu
 system.l2c.overall_accesses::cpu1.data         295642                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu2.dtb.walker        63431                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu2.itb.walker        13068                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst         409276                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst         409277                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu2.data         738486                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2646962                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2646963                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000482                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000583                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.000077                       # miss rate for ReadReq accesses
@@ -1586,28 +1586,28 @@ system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18654.411765
 system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12673.366834                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::total  9801.620860                       # average UpgradeReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75214.425979                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79174.213975                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 40432.856510                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79173.624917                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 40432.673214                       # average ReadExReq miss latency
 system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80759.847522                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 84690.734558                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 50643.712177                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 84693.071786                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 50644.643213                       # average ReadCleanReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83365.249781                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 86828.847987                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 47044.652254                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 86828.188018                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 47044.381634                       # average ReadSharedReq miss latency
 system.l2c.demand_avg_miss_latency::cpu1.inst 80759.847522                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.data 76374.653027                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 104635.135135                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu2.itb.walker        83000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 84690.734558                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 81093.784480                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 42528.236265                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 84693.071786                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 81093.177639                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 42528.130282                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.inst 80759.847522                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.data 76374.653027                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 104635.135135                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu2.itb.walker        83000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 84690.734558                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 81093.784480                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 42528.236265                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 84693.071786                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 81093.177639                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 42528.130282                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1671,28 +1671,28 @@ system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      7682000
 system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     12454500                       # number of UpgradeReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_latency::total     20136500                       # number of UpgradeReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1793331500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2818365000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   4611696500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2818341000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4611672500                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    222752000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    447335500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total    670087500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    447349500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total    670101500                       # number of ReadCleanReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    334839000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   1048084000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total   1382923000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   1048075000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total   1382914000                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.inst    222752000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.data   2128170500                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      3501500                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu2.itb.walker        73000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    447335500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   3866449000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6668281500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    447349500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   3866416000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6668262500                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.inst    222752000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.data   2128170500                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      3501500                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu2.itb.walker        73000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    447335500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   3866449000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6668281500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    447349500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   3866416000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6668262500                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28284583500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30647941500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::total  58932525000                       # number of ReadReq MSHR uncacheable cycles
@@ -1740,28 +1740,28 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22594.117647
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20861.809045                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21490.394877                       # average UpgradeReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65214.425979                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69174.213975                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 67578.565986                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69173.624917                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 67578.214296                       # average ReadExReq mshr miss latency
 system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70759.847522                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74692.853565                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73337.802342                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74695.191184                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73339.334574                       # average ReadCleanReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73365.249781                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 76855.906724                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75980.605461                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 76855.246755                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75980.110983                       # average ReadSharedReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70759.847522                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66374.653027                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 94635.135135                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker        73000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74692.853565                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71100.570063                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 69738.767805                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74695.191184                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71099.963222                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 69738.569098                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70759.847522                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66374.653027                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 94635.135135                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker        73000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74692.853565                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71100.570063                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 69738.767805                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74695.191184                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71099.963222                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 69738.569098                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152038.226472                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 149511.634884                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 150713.704820                       # average ReadReq mshr uncacheable latency
@@ -1831,7 +1831,7 @@ system.membus.reqLayer4.occupancy                4500                       # La
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer0.occupancy            1173000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1355053149                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1355052899                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.membus.respLayer4.occupancy           39163714                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
@@ -1848,47 +1848,47 @@ system.pc.south_bridge.ide.disks1.dma_write_full_pages            1
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
 system.toL2Bus.trans_dist::ReadReq            5228129                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           7456138                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           7456139                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             13940                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            13940                       # Transaction distribution
 system.toL2Bus.trans_dist::Writeback          1629241                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          974525                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          974526                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeReq            1670                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeResp           1670                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadExReq           290245                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadExResp          290245                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq        879201                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq        879202                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadSharedReq      1349341                       # Transaction distribution
 system.toL2Bus.trans_dist::MessageReq            1173                       # Transaction distribution
 system.toL2Bus.trans_dist::BadAddressError            3                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        20232                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2636643                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2636646                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     15081470                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        73733                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       221081                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              18012927                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     56268224                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              18012930                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     56268288                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213600772                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       270696                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       799584                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              270939276                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              270939340                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.snoops                          164260                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         10415382                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples         10415384                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::mean            1.028580                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::stdev           0.166622                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1               10117713     97.14%     97.14% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1               10117715     97.14%     97.14% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                 297669      2.86%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           10415382                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         2866107499                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           10415384                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         2866108499                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           340500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         884323704                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         884325204                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
 system.toL2Bus.respLayer1.occupancy        1946611318                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
index 33eef893cc9aea69b4f63738026ea8a06b162aa2..006ced44c4a8480b568b2396bcf536dc4629a742 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.417251                       # Number of seconds simulated
-sim_ticks                                417250627500                       # Number of ticks simulated
-final_tick                               417250627500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.417324                       # Number of seconds simulated
+sim_ticks                                417323825000                       # Number of ticks simulated
+final_tick                               417323825000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  80283                       # Simulator instruction rate (inst/s)
-host_op_rate                                   148451                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               40511385                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 420456                       # Number of bytes of host memory used
-host_seconds                                 10299.59                       # Real time elapsed on the host
+host_inst_rate                                  76614                       # Simulator instruction rate (inst/s)
+host_op_rate                                   141668                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               38666922                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 422964                       # Number of bytes of host memory used
+host_seconds                                 10792.79                       # Real time elapsed on the host
 sim_insts                                   826877109                       # Number of instructions simulated
 sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            222336                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24526912                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24749248                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       222336                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          222336                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18882944                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18882944                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3474                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             383233                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                386707                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          295046                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               295046                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               532860                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             58782205                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                59315065                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          532860                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             532860                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          45255640                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               45255640                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          45255640                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              532860                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            58782205                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              104570704                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        386709                       # Number of read requests accepted
-system.physmem.writeReqs                       295046                       # Number of write requests accepted
-system.physmem.readBursts                      386709                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     295046                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24728384                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     20992                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18881536                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24749376                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18882944                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      328                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            221888                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24526784                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24748672                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       221888                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          221888                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18880512                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18880512                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3467                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             383231                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                386698                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          295008                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               295008                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               531693                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             58771588                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                59303281                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          531693                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             531693                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          45241874                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               45241874                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          45241874                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              531693                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            58771588                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              104545155                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        386699                       # Number of read requests accepted
+system.physmem.writeReqs                       295008                       # Number of write requests accepted
+system.physmem.readBursts                      386699                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     295008                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24728192                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     20544                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18879296                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24748736                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18880512                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      321                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         188175                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               24066                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               26415                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               24733                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24594                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               23512                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23778                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24541                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24366                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23719                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23940                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24780                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24034                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23243                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         180081                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               24055                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               26417                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               24752                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24603                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               23500                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23758                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24527                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24383                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23721                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23953                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24767                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24050                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23223                       # Per bank write bursts
 system.physmem.perBankRdBursts::13              22939                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              23855                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              23866                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               18622                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               19926                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               18981                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               19010                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18166                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18514                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               19130                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               19080                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18668                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               18206                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              18899                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              17761                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              17398                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              16998                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              17806                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              17859                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              23841                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              23889                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               18611                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               19931                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               18984                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               19009                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18160                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18503                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               19127                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               19088                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18673                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               18215                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              18882                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              17760                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              17391                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              16992                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              17797                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              17866                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    417250612500                       # Total gap between requests
+system.physmem.totGap                    417323799500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  386709                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  386699                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 295046                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    381319                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4687                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       326                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        40                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 295008                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    381383                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      4594                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       347                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        45                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     6559                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    16925                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    17530                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    17602                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    17649                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17658                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17667                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17730                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17675                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    17721                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    17676                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    17739                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    17735                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    17731                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17918                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     6563                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    16946                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    17532                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    17611                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    17646                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17660                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17671                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17727                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17680                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17724                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17667                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17725                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    17729                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17716                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17891                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                    17608                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::32                    17539                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       34                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       20                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       17                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        7                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                       11                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        8                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        8                       # What write queue length does an incoming req see
@@ -193,40 +193,40 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       147516                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      295.624068                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     174.465729                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     322.989289                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          54788     37.14%     37.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        40113     27.19%     64.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        13739      9.31%     73.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7486      5.07%     78.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         5440      3.69%     82.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         3806      2.58%     84.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3042      2.06%     87.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2827      1.92%     88.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16275     11.03%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         147516                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17514                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        22.060866                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      217.469599                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17503     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            6      0.03%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            1      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       147629                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      295.379146                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     174.175505                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     323.147871                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          54960     37.23%     37.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        40188     27.22%     64.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13639      9.24%     73.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7424      5.03%     78.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         5455      3.70%     82.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         3764      2.55%     84.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3071      2.08%     87.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2858      1.94%     88.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16270     11.02%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         147629                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17513                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        22.062182                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      217.829565                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17502     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            5      0.03%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071            2      0.01%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-4095            2      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8192-9215            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::26624-27647            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17514                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17514                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.845038                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.773915                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.557012                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           17326     98.93%     98.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             134      0.77%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              31      0.18%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31               5      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           17513                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17513                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.844002                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.773318                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.551993                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           17314     98.86%     98.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             155      0.89%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              21      0.12%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31               6      0.03%     99.90% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::32-35               2      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               2      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               1      0.01%     99.92% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::40-43               1      0.01%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::44-47               1      0.01%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::48-51               1      0.01%     99.94% # Writes before turning the bus around for reads
@@ -239,202 +239,202 @@ system.physmem.wrPerTurnAround::100-103             1      0.01%     99.98% # Wr
 system.physmem.wrPerTurnAround::104-107             1      0.01%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::128-131             1      0.01%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::212-215             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17514                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4299952250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11544596000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1931905000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11128.79                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           17513                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4300618500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11545206000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1931890000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11130.60                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29878.79                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          59.27                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          45.25                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       59.32                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       45.26                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29880.60                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          59.25                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          45.24                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       59.30                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       45.24                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.82                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.46                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.35                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.85                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     317964                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    215920                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.29                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.18                       # Row buffer hit rate for writes
-system.physmem.avgGap                       612024.28                       # Average gap between requests
-system.physmem.pageHitRate                      78.35                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  570008880                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  311016750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1528831200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                981214560                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            27252713280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            63403052535                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           194733182250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             288780019455                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              692.103393                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   323396501250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     13932880000                       # Time in different power states
+system.physmem.avgRdQLen                         1.07                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        21.00                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     317874                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    215852                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.27                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.17                       # Row buffer hit rate for writes
+system.physmem.avgGap                       612174.73                       # Average gap between requests
+system.physmem.pageHitRate                      78.33                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  570560760                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  311317875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1528644000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                980994240                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            27257290320                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            63561829455                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           194635950000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             288846586650                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              692.146686                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   323236196500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     13935220000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     79920713750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     80148928000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  545189400                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  297474375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1484854800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                930437280                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            27252713280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            61562082780                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           196348068000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             288420819915                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              691.242519                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   326101005500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     13932880000                       # Time in different power states
+system.physmem_1.actEnergy                  545174280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  297466125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1484550600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                930119760                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            27257290320                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            61656237945                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           196307521500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             288478360530                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              691.264327                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   326031468000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     13935220000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     77215953250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     77353227000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               230048146                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         230048146                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           9737361                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            131481620                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               128745848                       # Number of BTB hits
+system.cpu.branchPred.lookups               230120124                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         230120124                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           9741646                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            131513055                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               128786829                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.919274                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                27747759                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1468593                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.927030                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                27739147                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1463012                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                        834501256                       # number of cpu cycles simulated
+system.cpu.numCycles                        834647651                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          185122313                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1269330935                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   230048146                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          156493607                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     638172933                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                20204179                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                        520                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                97554                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        807935                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles         1425                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles           52                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 179438196                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               2717621                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                       7                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          834304821                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.829912                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.382398                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          185096274                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1269602877                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   230120124                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          156525976                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     638307116                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                20224511                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                        639                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles               100012                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        833716                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles         1915                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles           31                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 179459099                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2721692                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       3                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          834451958                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.829961                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.382848                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                426682795     51.14%     51.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 33772943      4.05%     55.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 32839651      3.94%     59.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 33391032      4.00%     63.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 27218620      3.26%     66.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 27672975      3.32%     69.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 36987549      4.43%     74.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 33695145      4.04%     78.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                182044111     21.82%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                426852909     51.15%     51.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 33715610      4.04%     55.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 32892830      3.94%     59.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 33305005      3.99%     63.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 27242772      3.26%     66.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 27641402      3.31%     69.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 36945158      4.43%     74.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 33649224      4.03%     78.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                182207048     21.84%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            834304821                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.275671                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.521065                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                127569243                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             374855550                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 240395072                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              81382867                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               10102089                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2225227906                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               10102089                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                159580734                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               159860016                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          39443                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 285688559                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             219033980                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2175097177                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                169662                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents              136298138                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               24249327                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               48475339                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          2279313761                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5500897024                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3499022597                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             55311                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            834451958                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.275709                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.521124                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                127587811                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             374925225                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 240353691                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              81472976                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               10112255                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2225425956                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               10112255                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                159677255                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               160058551                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          39626                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 285629824                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             218934447                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2175227654                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                170665                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents              136328480                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               24447137                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               48120492                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          2279418477                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5501057674                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3499101319                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             56739                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                665272907                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               3132                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           2892                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 414765306                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            528353068                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           209871702                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         239280350                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         72161896                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2101070031                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               24820                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1826918488                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            398350                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       572106150                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    973941611                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          24268                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     834304821                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.189749                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.072611                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                665377623                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               3066                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           2844                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 415220487                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            528394625                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           209862852                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         239450332                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         72333056                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2101172761                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               24579                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1826985981                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            402337                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       572208639                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    974074914                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          24027                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     834451958                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.189444                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.072473                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           254655960     30.52%     30.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           125511852     15.04%     45.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           119464444     14.32%     59.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           111099885     13.32%     73.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            92302861     11.06%     84.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            61631743      7.39%     91.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            43068652      5.16%     96.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            19159370      2.30%     99.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             7410054      0.89%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           254736575     30.53%     30.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           125901135     15.09%     45.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           118815950     14.24%     59.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           111124108     13.32%     73.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            92771713     11.12%     84.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            61563159      7.38%     91.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            42999654      5.15%     96.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            19137261      2.29%     99.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             7402403      0.89%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       834304821                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       834451958                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                11329083     42.46%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               12292434     46.07%     88.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3060904     11.47%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                11322518     42.52%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     42.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               12255135     46.02%     88.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3050589     11.46%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2718358      0.15%      0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1211226700     66.30%     66.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               389616      0.02%     66.47% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               3881120      0.21%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 131      0.00%     66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2712800      0.15%      0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1211272172     66.30%     66.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               389805      0.02%     66.47% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               3881039      0.21%     66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 137      0.00%     66.68% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   2      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 24      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                 414      0.00%     66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 32      0.00%     66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                 438      0.00%     66.68% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.68% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.68% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.68% # Type of FU issued
@@ -456,84 +456,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.68% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.68% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.68% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            434992081     23.81%     90.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           173710042      9.51%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            435030017     23.81%     90.49% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           173699541      9.51%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1826918488                       # Type of FU issued
-system.cpu.iq.rate                           2.189234                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    26682421                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.014605                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4515190603                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2673460892                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1796856978                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               31965                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              70764                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses         6893                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1850867797                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   14754                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        185700457                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1826985981                       # Type of FU issued
+system.cpu.iq.rate                           2.188931                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    26628242                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.014575                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4515421528                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2673667500                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1796912005                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               32971                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              71974                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         7278                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1850886131                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   15292                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        185461351                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    144253147                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       213808                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       384332                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     60711516                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    144294331                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       211814                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       387366                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     60702666                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        18958                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           979                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        19327                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           950                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               10102089                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               107041835                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               6156081                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2101094851                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            396815                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             528355304                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            209871702                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               6976                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1865462                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               3396504                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         384332                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        5739761                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      4560590                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             10300351                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1805510192                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             428784370                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          21408296                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               10112255                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               107154683                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               6211386                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2101197340                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            397432                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             528396488                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            209862852                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               7002                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                1904351                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               3415285                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         387366                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        5743309                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      4569592                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             10312901                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1805578475                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             428811991                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          21407506                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    598976056                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                171763411                       # Number of branches executed
-system.cpu.iew.exec_stores                  170191686                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.163580                       # Inst execution rate
-system.cpu.iew.wb_sent                     1802107285                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1796863871                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1368034303                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2090148534                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    599002530                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                171769662                       # Number of branches executed
+system.cpu.iew.exec_stores                  170190539                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.163282                       # Inst execution rate
+system.cpu.iew.wb_sent                     1802166704                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1796919283                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1367983867                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2090000543                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.153219                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.654515                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.152908                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.654538                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       572186286                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       572288056                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           9823371                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    756648341                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.020739                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.547802                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           9830946                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    756741018                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.020491                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.547218                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    287852257     38.04%     38.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    175420323     23.18%     61.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     57242279      7.57%     68.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     86327184     11.41%     80.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     27107734      3.58%     83.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     27120897      3.58%     87.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      9790292      1.29%     88.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      8973905      1.19%     89.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     76813470     10.15%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    287828080     38.04%     38.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    175419007     23.18%     61.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     57379319      7.58%     68.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     86339033     11.41%     80.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     27139206      3.59%     83.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     27087573      3.58%     87.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      9812181      1.30%     88.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      8966770      1.18%     89.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     76769849     10.14%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    756648341                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    756741018                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
 system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -579,344 +579,344 @@ system.cpu.commit.op_class_0::MemWrite      149160186      9.76%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1528988701                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              76813470                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2781009858                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4280193893                       # The number of ROB writes
-system.cpu.timesIdled                            2297                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          196435                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              76769849                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   2781247926                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4280452547                       # The number of ROB writes
+system.cpu.timesIdled                            2275                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          195693                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
 system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.009220                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.009220                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.990864                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.990864                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2761953724                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1465013469                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      7172                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      467                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 600919347                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                409646269                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               990116456                       # number of misc regfile reads
+system.cpu.cpi                               1.009397                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.009397                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.990690                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.990690                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2761982517                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1465067529                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      7617                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      536                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 600891140                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                409637891                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               990175822                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2534268                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4088.021372                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           387614743                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2538364                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            152.702584                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           2534314                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4088.022771                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           387877466                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2538410                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            152.803316                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        1679458500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4088.021372                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  4088.022771                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.998052                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.998052                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          878                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3164                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          875                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3167                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         784355902                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        784355902                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    238963393                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       238963393                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148180513                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148180513                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     387143906                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        387143906                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    387143906                       # number of overall hits
-system.cpu.dcache.overall_hits::total       387143906                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2785174                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2785174                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       979689                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       979689                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3764863                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3764863                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3764863                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3764863                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  59469395500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  59469395500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  30831236499                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  30831236499                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  90300631999                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  90300631999                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  90300631999                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  90300631999                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    241748567                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    241748567                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         784886120                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        784886120                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    239229080                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       239229080                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148188693                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      148188693                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     387417773                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        387417773                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    387417773                       # number of overall hits
+system.cpu.dcache.overall_hits::total       387417773                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2784573                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2784573                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       971509                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       971509                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3756082                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3756082                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3756082                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3756082                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  59403884000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  59403884000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  30555866498                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  30555866498                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  89959750498                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  89959750498                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  89959750498                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  89959750498                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    242013653                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    242013653                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    390908769                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    390908769                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    390908769                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    390908769                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011521                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.011521                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006568                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.006568                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009631                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009631                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009631                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009631                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21352.129346                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 21352.129346                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31470.432453                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31470.432453                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23985.104371                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23985.104371                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23985.104371                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23985.104371                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        10830                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets           28                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              1133                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.558694                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets            7                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    391173855                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    391173855                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    391173855                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    391173855                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011506                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.011506                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006513                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.006513                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009602                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009602                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009602                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009602                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21333.211232                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 21333.211232                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31451.964416                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31451.964416                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23950.422408                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23950.422408                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23950.422408                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23950.422408                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        11511                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets           19                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              1175                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.796596                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     9.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2332705                       # number of writebacks
-system.cpu.dcache.writebacks::total           2332705                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1017213                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1017213                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        19267                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        19267                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1036480                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1036480                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1036480                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1036480                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1767961                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1767961                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       960422                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       960422                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2728383                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2728383                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2728383                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2728383                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33609753000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  33609753000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  29619647000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  29619647000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  63229400000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  63229400000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  63229400000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  63229400000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007313                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007313                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006439                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006439                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006980                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006980                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006980                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006980                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19010.460638                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19010.460638                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30840.242102                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30840.242102                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23174.678922                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23174.678922                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23174.678922                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23174.678922                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2332789                       # number of writebacks
+system.cpu.dcache.writebacks::total           2332789                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1016577                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1016577                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        19222                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        19222                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1035799                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1035799                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1035799                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1035799                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1767996                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1767996                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       952287                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       952287                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2720283                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2720283                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2720283                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2720283                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33610922500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  33610922500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  29353562500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  29353562500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  62964485000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  62964485000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  62964485000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  62964485000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007305                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007305                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006384                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006384                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006954                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006954                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006954                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006954                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19010.745782                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19010.745782                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30824.281440                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30824.281440                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23146.299484                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23146.299484                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23146.299484                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23146.299484                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              6976                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1050.495149                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           179233953                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              8576                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          20899.481460                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              6923                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1052.839931                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           179263061                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              8530                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          21015.599179                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1050.495149                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.512937                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.512937                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1600                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1052.839931                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.514082                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.514082                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1607                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           46                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          313                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1156                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.781250                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         359075141                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        359075141                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    179236865                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       179236865                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     179236865                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        179236865                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    179236865                       # number of overall hits
-system.cpu.icache.overall_hits::total       179236865                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       201330                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        201330                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       201330                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         201330                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       201330                       # number of overall misses
-system.cpu.icache.overall_misses::total        201330                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1280282499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1280282499                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1280282499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1280282499                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1280282499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1280282499                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    179438195                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    179438195                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    179438195                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    179438195                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    179438195                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    179438195                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001122                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001122                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.001122                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.001122                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.001122                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.001122                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6359.124318                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  6359.124318                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  6359.124318                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  6359.124318                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  6359.124318                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  6359.124318                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          947                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets           40                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::2           42                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          311                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1171                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.784668                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         359108705                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        359108705                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    179266033                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       179266033                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     179266033                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        179266033                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    179266033                       # number of overall hits
+system.cpu.icache.overall_hits::total       179266033                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       193066                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        193066                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       193066                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         193066                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       193066                       # number of overall misses
+system.cpu.icache.overall_misses::total        193066                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1248536999                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1248536999                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1248536999                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1248536999                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1248536999                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1248536999                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    179459099                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    179459099                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    179459099                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    179459099                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    179459099                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    179459099                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001076                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.001076                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.001076                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.001076                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.001076                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.001076                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6466.892146                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  6466.892146                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  6466.892146                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  6466.892146                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  6466.892146                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  6466.892146                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          984                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    63.133333                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets           40                       # average number of cycles each access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    65.600000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2576                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2576                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2576                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2576                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2576                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2576                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       198754                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       198754                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       198754                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       198754                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       198754                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       198754                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    967804499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    967804499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    967804499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    967804499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    967804499                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    967804499                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001108                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001108                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001108                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.001108                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001108                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.001108                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4869.358599                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  4869.358599                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4869.358599                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  4869.358599                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4869.358599                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  4869.358599                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2556                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2556                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2556                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2556                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2556                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2556                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       190510                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       190510                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       190510                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       190510                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       190510                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       190510                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    942973499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    942973499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    942973499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    942973499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    942973499                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    942973499                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001062                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001062                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001062                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.001062                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001062                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.001062                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4949.732292                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  4949.732292                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4949.732292                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  4949.732292                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4949.732292                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  4949.732292                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           354031                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29616.745203                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3899360                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           386379                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.092060                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     197715227000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 20955.071178                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   251.225127                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8410.448899                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.639498                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007667                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.256667                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.903831                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32348                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements           354021                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29616.675040                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3899591                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           386376                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.092736                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     197713230000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 20957.443658                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   250.582098                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  8408.649283                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.639570                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007647                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.256612                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.903829                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32355                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          240                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13348                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18673                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987183                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         43294513                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        43294513                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      2332705                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2332705                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         1885                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         1885                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       564153                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       564153                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         5133                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         5133                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1590938                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1590938                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         5133                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2155091                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2160224                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         5133                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2155091                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2160224                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data       188135                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total       188135                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       206662                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       206662                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3478                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3478                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       176611                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       176611                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3478                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       383273                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        386751                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3478                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       383273                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       386751                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     13341000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     13341000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16380998500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  16380998500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    281189000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    281189000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  14213384500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  14213384500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    281189000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  30594383000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  30875572000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    281189000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  30594383000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  30875572000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      2332705                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2332705                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data       190020                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total       190020                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       770815                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       770815                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         8611                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         8611                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1767549                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1767549                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         8611                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2538364                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2546975                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         8611                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2538364                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2546975                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.990080                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.990080                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268108                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.268108                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.403902                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.403902                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.099919                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.099919                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.403902                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.150992                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.151847                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.403902                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.150992                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.151847                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    70.911845                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    70.911845                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79264.685815                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79264.685815                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80847.901093                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80847.901093                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80478.478124                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80478.478124                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80847.901093                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79823.997516                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79833.205344                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80847.901093                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79823.997516                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79833.205344                       # average overall miss latency
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13362                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18669                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987396                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         43228510                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        43228510                       # Number of data accesses
+system.cpu.l2cache.Writeback_hits::writebacks      2332789                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2332789                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         1839                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         1839                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       564112                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       564112                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         5045                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         5045                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1591020                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1591020                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         5045                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2155132                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2160177                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         5045                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2155132                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2160177                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data       180034                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total       180034                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       206676                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       206676                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3470                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3470                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       176602                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       176602                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3470                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       383278                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        386748                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3470                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       383278                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       386748                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     13120000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     13120000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16380232500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  16380232500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    280484500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    280484500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  14214843500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  14214843500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    280484500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  30595076000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  30875560500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    280484500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  30595076000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  30875560500                       # number of overall miss cycles
+system.cpu.l2cache.Writeback_accesses::writebacks      2332789                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2332789                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data       181873                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total       181873                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       770788                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       770788                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         8515                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         8515                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1767622                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1767622                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         8515                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2538410                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2546925                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         8515                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2538410                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2546925                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989889                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989889                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268136                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.268136                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.407516                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.407516                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.099909                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.099909                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.407516                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.150991                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.151849                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.407516                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.150991                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.151849                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    72.875124                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    72.875124                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79255.610231                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79255.610231                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80831.268012                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80831.268012                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80490.840987                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80490.840987                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80831.268012                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79824.764270                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 79833.794874                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80831.268012                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79824.764270                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79833.794874                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -925,136 +925,136 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       295046                       # number of writebacks
-system.cpu.l2cache.writebacks::total           295046                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       295008                       # number of writebacks
+system.cpu.l2cache.writebacks::total           295008                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         2001                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         2001                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       188135                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total       188135                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206662                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       206662                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3477                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3477                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       176611                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       176611                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3477                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       383273                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       386750                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3477                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       383273                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       386750                       # number of overall MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   3958974717                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   3958974717                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14314378500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14314378500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    246372000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    246372000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12447274500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12447274500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    246372000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26761653000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  27008025000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    246372000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26761653000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  27008025000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1987                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total         1987                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       180034                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total       180034                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206676                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       206676                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3469                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3469                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       176602                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       176602                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3469                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       383278                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       386747                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3469                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       383278                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       386747                       # number of overall MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   3787147939                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   3787147939                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14313472500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14313472500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    245748000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    245748000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12448823500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12448823500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    245748000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26762296000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  27008044000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    245748000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26762296000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  27008044000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.990080                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.990080                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268108                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268108                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.403786                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.403786                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.099919                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.099919                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.403786                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150992                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.151847                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.403786                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150992                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.151847                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21043.265299                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21043.265299                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69264.685815                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69264.685815                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70857.635893                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70857.635893                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70478.478124                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70478.478124                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70857.635893                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69823.997516                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69833.290239                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70857.635893                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69823.997516                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69833.290239                       # average overall mshr miss latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.989889                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.989889                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268136                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268136                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.407399                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.407399                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.099909                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.099909                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.407399                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150991                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.151849                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.407399                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150991                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.151849                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21035.737355                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21035.737355                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69255.610231                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69255.610231                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70841.164601                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70841.164601                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70490.840987                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70490.840987                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70841.164601                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69824.764270                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69833.881064                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70841.164601                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69824.764270                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69833.881064                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp       1966300                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2627751                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       256160                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq       190020                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp       190020                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       770815                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       770815                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       198754                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1767549                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       213879                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7980131                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8194010                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       550912                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311748416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          312299328                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      544174                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      5822413                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.060805                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.238972                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       1958129                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2627797                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       256061                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq       181873                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp       181873                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       770788                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       770788                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       190510                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1767622                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       205493                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7963932                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8169425                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       544768                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311756736                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          312301504                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      536016                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5806051                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.060974                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.239284                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            5468382     93.92%     93.92% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             354031      6.08%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            5452030     93.90%     93.90% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             354021      6.10%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5822413                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5094765649                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        5806051                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5085061879                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     298130492                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     285765490                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3902557066                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3898552059                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             180085                       # Transaction distribution
-system.membus.trans_dist::Writeback            295046                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            57422                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           188175                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          188175                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206622                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206622                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        180087                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1502234                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1502234                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1502234                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43632192                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43632192                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                43632192                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp             180069                       # Transaction distribution
+system.membus.trans_dist::Writeback            295008                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            57429                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           180081                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          180081                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206629                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206629                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        180070                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1485996                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1485996                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1485996                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43629184                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43629184                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                43629184                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            927352                       # Request fanout histogram
+system.membus.snoop_fanout::samples            919217                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  927352    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  919217    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              927352                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          2233095783                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              919217                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          2221438059                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2421970141                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2405709985                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------