radv: fix GPU hangs when loading depth/stencil clear values on SI/CIK

HTILE is supported on these chips, not sure how I missed that.
This restores using PFP_SYNC_ME when LOAD_CONTEXT_REG is not used.

Fixes: f425d9ee74 ("radv: use LOAD_CONTEXT_REG when loading fast clear values")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 9fd9e81b3c1fa2849d48df7ac4b88ddacc500666..ee5373950f68ad788328e2d5ae527071474598a5 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1317,11 +1317,25 @@ radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
 
        uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
 
-       radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
-       radeon_emit(cs, va);
-       radeon_emit(cs, va >> 32);
-       radeon_emit(cs, (reg >> 2) - CONTEXT_SPACE_START);
-       radeon_emit(cs, reg_count);
+       if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
+               radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
+               radeon_emit(cs, va);
+               radeon_emit(cs, va >> 32);
+               radeon_emit(cs, (reg >> 2) - CONTEXT_SPACE_START);
+               radeon_emit(cs, reg_count);
+       } else {
+               radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
+               radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
+                               COPY_DATA_DST_SEL(COPY_DATA_REG) |
+                               (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
+               radeon_emit(cs, va);
+               radeon_emit(cs, va >> 32);
+               radeon_emit(cs, reg >> 2);
+               radeon_emit(cs, 0);
+
+               radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
+               radeon_emit(cs, 0);
+       }
 }
 
 /*