else:
sources += syscall_emulation_sources
-extra_libraries = []
-env.Append(LIBS=['z'])
-if isdir('/usr/lib64/mysql') or isdir('/usr/lib/mysql') or \
- isdir('/usr/local/lib/mysql'):
- print 'Compiling with MySQL support!'
- env.Append(LIBPATH=['/usr/lib64/mysql', '/usr/local/lib/mysql/',
- '/usr/lib/mysql'])
- env.Append(CPPPATH=['/usr/local/include/mysql', '/usr/include/mysql'])
+if env['USE_MYSQL']:
sources += mysql_sources
- env.Append(CPPDEFINES = 'USE_MYSQL')
- env.Append(CPPDEFINES = 'STATS_BINNING')
- env.Append(LIBS=['mysqlclient'])
+
+for opt in env.ExportOptions:
+ env.ConfigFile(opt)
###################################################
#
date_obj = env.Object('base/date.cc')
env.Depends(date_obj, objs)
objs.append(date_obj)
- objs.extend(extra_libraries)
return objs
###################################################
#include "base/inifile.hh"
#include "base/str.hh"
#include "base/trace.hh"
+#include "config/alpha_tlaser.hh"
#include "cpu/exec_context.hh"
#include "sim/builder.hh"
*/
-#ifdef ALPHA_TLASER
+#if ALPHA_TLASER
if (req->paddr & PAddrUncachedBit39) {
#else
if (req->paddr & PAddrUncachedBit43) {
// mark request as uncacheable
req->flags |= UNCACHEABLE;
-#ifndef ALPHA_TLASER
+#if !ALPHA_TLASER
// Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
req->paddr &= PAddrUncachedMask;
#endif
// VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
// VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
-#ifdef ALPHA_TLASER
+#if ALPHA_TLASER
if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
VAddrSpaceEV5(req->vaddr) == 2) {
#else
req->paddr = req->vaddr & PAddrImplMask;
-#ifndef ALPHA_TLASER
+#if !ALPHA_TLASER
// sign extend the physical address properly
if (req->paddr & PAddrUncachedBit40)
req->paddr |= ULL(0xf0000000000);
}
// Check for "superpage" mapping
-#ifdef ALPHA_TLASER
+#if ALPHA_TLASER
if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
VAddrSpaceEV5(req->vaddr) == 2) {
#else
req->paddr = req->vaddr & PAddrImplMask;
-#ifndef ALPHA_TLASER
+#if !ALPHA_TLASER
// sign extend the physical address properly
if (req->paddr & PAddrUncachedBit40)
req->paddr |= ULL(0xf0000000000);
#include "base/kgdb.h"
#include "base/remote_gdb.hh"
#include "base/stats/events.hh"
+#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/exec_context.hh"
#include "cpu/fast/cpu.hh"
#include "sim/debug.hh"
#include "sim/sim_events.hh"
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
using namespace EV5;
#ifndef __ARCH_ALPHA_EV5_HH__
#define __ARCH_ALPHA_EV5_HH__
+#include "config/alpha_tlaser.hh"
+
namespace EV5 {
-#ifdef ALPHA_TLASER
+#if ALPHA_TLASER
const uint64_t AsnMask = ULL(0x7f);
#else
const uint64_t AsnMask = ULL(0xff);
inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
-#ifdef ALPHA_TLASER
+#if ALPHA_TLASER
inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); }
const int PAddrImplBits = 40;
#else
const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
inline Addr Phys2K0Seg(Addr addr)
{
-#ifndef ALPHA_TLASER
+#if !ALPHA_TLASER
if (addr & PAddrUncachedBit43) {
addr &= PAddrUncachedMask;
addr |= PAddrUncachedBit40;
#include <iostream>
#include <iomanip>
+#include "config/ss_compatible_fp.hh"
#include "cpu/static_inst.hh"
#include "mem/mem_req.hh" // some constructors use MemReq flags
}};
output decoder {{
#include "base/cprintf.hh"
+#include "base/fenv.hh"
#include "base/loader/symtab.hh"
+#include "config/ss_compatible_fp.hh"
#include "cpu/exec_context.hh" // for Jump::branchTarget()
#include <math.h>
-#if defined(linux)
-#include <fenv.h>
-#endif
}};
output exec {{
#include <math.h>
-#if defined(linux)
-#include <fenv.h>
-#endif
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
#include "arch/alpha/pseudo_inst.hh"
#endif
+#include "base/fenv.hh"
+#include "config/ss_compatible_fp.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "sim/sim_exit.hh"
/// instruction in full-system mode.
/// @retval Full-system mode: No_Fault if FP is enabled, Fen_Fault
/// if not. Non-full-system mode: always returns No_Fault.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
Fault fault = No_Fault; // dummy... this ipr access should not fault
};
protected:
-#if defined(linux)
+ /// Map Alpha rounding mode to C99 constants from <fenv.h>.
static const int alphaToC99RoundingMode[];
-#endif
/// Map enum RoundingMode values to disassembly suffixes.
static const char *roundingModeSuffix[];
}
}
-#if defined(linux)
int getC99RoundingMode(uint64_t fpcr_val) const;
-#endif
// This differs from the AlphaStaticInst version only in
// printing suffixes for non-default rounding & trapping modes.
}};
output decoder {{
-#if defined(linux)
int
AlphaFP::getC99RoundingMode(uint64_t fpcr_val) const
{
return alphaToC99RoundingMode[roundingMode];
}
}
-#endif
std::string
AlphaFP::generateDisassembly(Addr pc, const SymbolTable *symtab) const
return ss.str();
}
-#if defined(linux)
const int AlphaFP::alphaToC99RoundingMode[] = {
FE_TOWARDZERO, // Chopped
FE_DOWNWARD, // Minus_Infinity
FE_TONEAREST, // Normal
FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
};
-#endif
const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
// mark invalid trapping modes, but don't fail on them, because
exec_output = BasicExecute.subst(fast_iop)
gen_code_prefix = r'''
-#if defined(linux)
fesetround(getC99RoundingMode(xc->readFpcr()));
-#endif
'''
+
gen_code_suffix = r'''
-#if defined(linux)
fesetround(FE_TONEAREST);
-#endif
'''
gen_iop = InstObjParams(name, Name + 'General', 'AlphaFP',
1: decode INTIMM {
// return EV5 for FULL_SYSTEM and EV6 otherwise
1: implver({{
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
Rc = 1;
#else
Rc = 2;
}
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
// The mysterious 11.25...
0x25: WarnUnimpl::eleven25();
#endif
0xb: decode FA {
31: decode FP_TYPEFUNC {
format FloatingPointOperate {
-#ifdef SS_COMPATIBLE_FP
+#if SS_COMPATIBLE_FP
0x0b: sqrts({{
if (Fb < 0.0)
fault = Arithmetic_Fault;
// and source type.
0: decode FP_TYPEFUNC {
format FloatingPointOperate {
-#ifdef SS_COMPATIBLE_FP
+#if SS_COMPATIBLE_FP
0x00: adds({{ Fc = Fa + Fb; }});
0x01: subs({{ Fc = Fa - Fb; }});
0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
format BasicOperate {
0xc000: rpcc({{
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
/* Rb is a fake dependency so here is a fun way to get
* the parser to understand that.
*/
0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
format BasicOperate {
0xe000: rc({{
Ra = xc->readIntrFlag();
#endif
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
0x00: CallPal::call_pal({{
if (!palValid ||
(palPriv
}
#endif
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
format HwLoadStore {
0x1b: decode HW_LDST_QUAD {
0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
#include "arch/alpha/faults.hh"
#include "base/misc.hh"
+#include "config/full_system.hh"
#include "sim/host.hh"
class FastCPU;
static const Addr PageMask = ~(PageBytes - 1);
static const Addr PageOffset = PageBytes - 1;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
typedef uint64_t InternalProcReg;
MiscRegFile miscRegs; // control register file
Addr pc; // program counter
Addr npc; // next-cycle program counter
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
IntReg palregs[NumIntRegs]; // PAL shadow registers
InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
int intrflag; // interrupt flag
const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
const int MaxAddr = (Addr)-1;
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
class SyscallReturn {
public:
template <class T>
#endif
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
typedef TheISA::InternalProcReg InternalProcReg;
const int NumInternalProcRegs = TheISA::NumInternalProcRegs;
const int NumInterruptLevels = TheISA::NumInterruptLevels;
// (by bucket).
// #define FAST_ALLOC_STATS
-#ifdef NO_FAST_ALLOC
+#include "config/no_fast_alloc.hh"
+
+#if NO_FAST_ALLOC
class FastAlloc {
};
--- /dev/null
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __BASE_FENV_HH__
+#define __BASE_FENV_HH__
+
+#include "config/use_fenv.hh"
+
+#if USE_FENV
+
+#include <fenv.h>
+
+#else
+
+// Dummy definitions to allow code to compile w/o a real <fenv.h>.
+
+#define FE_TONEAREST 0
+#define FE_DOWNWARD 0
+#define FE_UPWARD 0
+#define FE_TOWARDZERO 0
+
+inline int fesetround(int rounding_mode) { return 0; }
+
+#endif // USE_FENV
+
+
+#endif // __BASE_FENV_HH__
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __BASE_MYQSL_HH__
-#define __BASE_MYQSL_HH__
+#ifndef __BASE_MYSQL_HH__
+#define __BASE_MYSQL_HH__
#define TO_BE_INCLUDED_LATER 0
/* namespace MySQL */ }
-#endif // __BASE_MYQSL_HH__
+#endif // __BASE_MYSQL_HH__
#include "base/time.hh"
#include "base/trace.hh"
#include "base/stats/statdb.hh"
+#include "config/stats_binning.hh"
using namespace std;
Database::stats().sort(StatData::less);
-#if defined(STATS_BINNING)
+#if STATS_BINNING
if (MainBin::curBin() == NULL) {
static MainBin mainBin("main bin");
mainBin.activate();
#include "base/stats/flags.hh"
#include "base/stats/visit.hh"
#include "base/stats/types.hh"
+#include "config/stats_binning.hh"
#include "sim/host.hh"
class Callback;
* binned. If the typedef is NoBin, nothing is binned. If it is
* MainBin, then all stats are binned under that Bin.
*/
-#if defined(STATS_BINNING)
+#if STATS_BINNING
typedef MainBin DefaultBin;
#else
typedef NoBin DefaultBin;
#include <vector>
-#ifdef USE_MYSQL
+#include "base/stats/events.hh"
+
+#if USE_MYSQL
#include "base/cprintf.hh"
#include "base/misc.hh"
#include "base/mysql.hh"
-#include "base/stats/events.hh"
#include "base/stats/mysql.hh"
#include "base/stats/mysql_run.hh"
#include "base/str.hh"
ObjectMatch event_ignore;
-#ifdef USE_MYSQL
+#if USE_MYSQL
class InsertEvent
{
private:
#include <string>
#include "base/trace.hh"
+#include "config/use_mysql.hh"
namespace Stats {
extern Tick EventStart;
-#ifdef USE_MYSQL
+#if USE_MYSQL
void __event(const std::string &stat);
bool MySqlConnected();
#endif
DPRINTF(StatEvents, "Statistics Event: %s\n", stat);
-#ifdef USE_MYSQL
+#if USE_MYSQL
if (!MySqlConnected())
return;
import sys
import os
-# Check for recent-enough Python version
-(major, minor) = sys.version_info[:2]
-if major < 2 or (major == 2 and minor < 3):
- print "Error: M5 requires Python 2.3 or later."
- sys.exit(1)
+# Check for recent-enough Python and SCons versions
+EnsurePythonVersion(2,3)
+EnsureSConsVersion(0,96)
# The absolute path to the current directory (where this file lives).
ROOT = Dir('.').abspath
# Check for 'm5' and 'ext' links, die if they don't exist.
if not os.path.isdir(SRCDIR):
print "Error: '%s' must be a link to the M5 source tree." % SRCDIR
- sys.exit(1)
+ Exit(1)
if not os.path.isdir('ext'):
print "Error: '%s' must be a link to the M5 external source tree." \
% EXT_SRCDIR
- sys.exit(1)
+ Exit(1)
# tell python where to find m5 python code
sys.path.append(os.path.join(SRCDIR, 'python'))
-
-###################################################
-#
-# Define Configurations
-#
-# The build system infers the build options from the subdirectory name
-# that the simulator is built under. The subdirectory name must be of
-# the form <CONFIG>[.<OPT>]*, where <CONFIG> is a base configuration
-# (e.g., ALPHA_SE or ALPHA_FS) and OPT is an option (e.g., MYSQL). The
-# following code defines the standard configurations and options.
-# Additional local configurations and options are read from the file
-# 'local_configs' if it exists.
-#
-# Each base configuration or option is defined in two steps: a
-# function that takes an SCons build environment and modifies it
-# appropriately for that config or option, and an entry in the
-# 'configs_map' or 'options_map' dictionary that maps the directory
-# name string to the function. (The directory names are all upper
-# case, by convention.)
-#
-###################################################
-
-# Base non-full-system Alpha ISA configuration.
-def AlphaSyscallEmulConfig(env):
- env.Replace(TARGET_ISA = 'alpha')
- env.Append(CPPDEFINES = 'SS_COMPATIBLE_FP')
-
-# Base full-system configuration.
-def AlphaFullSysConfig(env):
- env.Replace(TARGET_ISA = 'alpha')
- env.Replace(FULL_SYSTEM = True)
- env.Append(CPPDEFINES = ['FULL_SYSTEM'])
-
-# Base configurations map.
-configs_map = {
- 'ALPHA_SE' : AlphaSyscallEmulConfig,
- 'ALPHA_FS' : AlphaFullSysConfig
- }
-
-# Disable FastAlloc object allocation.
-def NoFastAllocOpt(env):
- env.Append(CPPDEFINES = 'NO_FAST_ALLOC')
-
-# Enable efence
-def EfenceOpt(env):
- env.Append(LIBS=['efence'])
-
-# Configuration options map.
-options_map = {
- 'NO_FAST_ALLOC' : NoFastAllocOpt,
- 'EFENCE' : EfenceOpt
- }
-
-# The 'local_configs' file can be used to define additional base
-# configurations and/or options without changing this file.
-if os.path.isfile('local_configs'):
- SConscript('local_configs', exports = ['configs_map', 'options_map'])
-
-# This function parses a directory name of the form <CONFIG>[.<OPT>]*
-# and sets up the build environment appropriately. Returns True if
-# successful, False if the base config or any of the options were not
-# defined.
-def set_dir_options(dir, env):
- parts = dir.split('.')
- config = parts[0]
- opts = parts[1:]
- try:
- configs_map[config](env)
- map(lambda opt: options_map[opt](env), opts)
- return True
- except KeyError, key:
- print "Config/option '%s' not found." % key
- return False
-
-# Set the default configuration and binary. The default target (if
-# scons is invoked at the top level with no command-line targets) is
-# 'ALPHA_SE/m5.debug'. If scons is invoked in a subdirectory with no
-# command-line targets, the configuration
-
###################################################
#
# Figure out which configurations to set up.
if not launch_dir.startswith(ROOT):
print "Error: launch dir (%s) not a subdirectory of ROOT (%s)!" \
(launch_dir, ROOT)
- sys.exit(1)
+ Exit(1)
# make launch_dir relative to ROOT (strip ROOT plus slash off front)
launch_dir = launch_dir[len(ROOT)+1:]
if len(COMMAND_LINE_TARGETS) != 0:
if dir not in build_dirs:
build_dirs.append(dir)
+# Make a first pass to verify that build dirs are valid
+for build_dir in build_dirs:
+ if not os.path.isdir(build_dir):
+ print "Error: build directory", build_dir, "does not exist."
+ Exit(1)
+
###################################################
#
# Set up the default build environment. This environment is copied
#
###################################################
-default_env = Environment(ENV = os.environ, # inherit user's enviroment vars
- ROOT = ROOT,
- SRCDIR = SRCDIR,
- EXT_SRCDIR = EXT_SRCDIR,
- CPPDEFINES = [],
- FULL_SYSTEM = False,
- ALPHA_TLASER = False,
- USE_MYSQL = False)
+env = Environment(ENV = os.environ, # inherit user's environment vars
+ ROOT = ROOT,
+ SRCDIR = SRCDIR,
+ EXT_SRCDIR = EXT_SRCDIR)
-default_env.SConsignFile("sconsign")
+env.SConsignFile("sconsign")
-# For some reason, the CC and CXX variables don't get passed into the
-# environment correctly. This is probably some sort of scons bug that
-# will eventually be fixed.
if os.environ.has_key('CC'):
- default_env.Replace(CC=os.environ['CC'])
+ env.Replace(CC=os.environ['CC'])
if os.environ.has_key('CXX'):
- default_env.Replace(CXX=os.environ['CXX'])
+ env.Replace(CXX=os.environ['CXX'])
# M5_EXT is used by isa_parser.py to find the PLY package.
-default_env.Append(ENV = { 'M5_EXT' : EXT_SRCDIR })
+env.Append(ENV = { 'M5_EXT' : EXT_SRCDIR })
-default_env.Append(CCFLAGS='-pipe')
-default_env.Append(CCFLAGS='-fno-strict-aliasing')
-default_env.Append(CCFLAGS=Split('-Wall -Wno-sign-compare -Werror -Wundef'))
+# Set up default C++ compiler flags
+env.Append(CCFLAGS='-pipe')
+env.Append(CCFLAGS='-fno-strict-aliasing')
+env.Append(CCFLAGS=Split('-Wall -Wno-sign-compare -Werror -Wundef'))
if sys.platform == 'cygwin':
# cygwin has some header file issues...
- default_env.Append(CCFLAGS=Split("-Wno-uninitialized"))
-default_env.Append(CPPPATH=[os.path.join(EXT_SRCDIR + '/dnet')])
+ env.Append(CCFLAGS=Split("-Wno-uninitialized"))
+env.Append(CPPPATH=[os.path.join(EXT_SRCDIR + '/dnet')])
-# libelf build is described in its own SConscript file. Using a
-# dictionary for exports lets us export "default_env" so the
-# SConscript will see it as "env". SConscript-global is the build in
-# build/libelf shared among all configs.
-default_env.SConscript('m5/libelf/SConscript-global',
- exports={'env' : default_env})
+# Default libraries
+env.Append(LIBS=['z'])
+
+# Platform-specific configuration
+conf = Configure(env)
+
+# Check for <fenv.h> (C99 FP environment control)
+have_fenv = conf.CheckHeader('fenv.h', '<>')
+if not have_fenv:
+ print "Warning: Header file <fenv.h> not found."
+ print " This host has no IEEE FP rounding mode control."
+
+# Check for mysql
+mysql_config = WhereIs('mysql_config')
+have_mysql = mysql_config != None
+
+env = conf.Finish()
+
+# The source operand is a Value node containing the value of the option.
+def build_config_file(target, source, env, option):
+ f = file(str(target[0]), 'w')
+ print >> f, '#define', option, source[0]
+ f.close()
+ return None
+
+def config_builder(env, option):
+ target = os.path.join('config', option.lower() + '.hh')
+ source = Value(env[option])
+ def my_build_config_file(target, source, env):
+ build_config_file(target, source, env, option)
+ env.Command(target, source, my_build_config_file)
+
+env.Append(BUILDERS = { 'ConfigFile' : config_builder })
+
+# libelf build is described in its own SConscript file.
+# SConscript-global is the build in build/libelf shared among all
+# configs.
+env.SConscript('m5/libelf/SConscript-global', exports = 'env')
###################################################
#
#
###################################################
+# rename base env
+base_env = env
+
for build_dir in build_dirs:
# Make a copy of the default environment to use for this config.
- env = default_env.Copy()
- # Modify 'env' according to the build directory config.
- print "Configuring options for directory '%s'." % build_dir
- if not set_dir_options(build_dir, env):
- print "Skipping directory '%s'." % build_dir
- continue
-
+ env = base_env.Copy()
+ # Set env according to the build directory config.
+ options_file = os.path.join(build_dir, 'build_options')
+ opts = Options(options_file, ARGUMENTS)
+ opts.AddOptions(
+ EnumOption('TARGET_ISA', 'Target ISA', 'alpha', ('alpha')),
+ BoolOption('FULL_SYSTEM', 'Full-system support', False),
+ BoolOption('ALPHA_TLASER',
+ 'Model Alpha TurboLaser platform (vs. Tsunami)', False),
+ BoolOption('NO_FAST_ALLOC', 'Disable fast object allocator', False),
+ BoolOption('EFENCE', 'Link with Electric Fence malloc debugger',
+ False),
+ BoolOption('SS_COMPATIBLE_FP',
+ 'Make floating-point results compatible with SimpleScalar',
+ False),
+ BoolOption('STATS_BINNING', 'Bin statistics by CPU mode', have_mysql),
+ BoolOption('USE_MYSQL', 'Use MySQL for stats output', have_mysql),
+ BoolOption('USE_FENV', 'Use <fenv.h> IEEE mode control', have_fenv)
+ )
+
+ opts.Update(env)
+ opts.Save(options_file, env)
+
+ env.ExportOptions = ['FULL_SYSTEM', 'ALPHA_TLASER', 'USE_FENV', \
+ 'USE_MYSQL', 'NO_FAST_ALLOC', 'SS_COMPATIBLE_FP', \
+ 'STATS_BINNING']
+
+ # Process option settings.
+
+ if not have_fenv and env['USE_FENV']:
+ print "Warning: <fenv.h> not available; " \
+ "forcing USE_FENV to False in", build_dir + "."
+ env['USE_FENV'] = False
+
+ if not env['USE_FENV']:
+ print "Warning: No IEEE FP rounding mode control in", build_dir + "."
+ print " FP results may deviate slightly", \
+ "and some regression tests may fail."
+
+ if env['EFENCE']:
+ env.Append(LIBS=['efence'])
+
+ if env['USE_MYSQL']:
+ if not have_mysql:
+ print "Warning: MySQL not available; " \
+ "forcing USE_MYSQL to False in", build_dir + "."
+ env['USE_MYSQL'] = False
+ else:
+ print "Compiling in", build_dir, "with MySQL support."
+ env.ParseConfig(mysql_config + ' --libs')
+ env.ParseConfig(mysql_config + ' --include')
+
# The m5/SConscript file sets up the build rules in 'env' according
# to the configured options.
SConscript('m5/SConscript', build_dir = build_dir, exports = 'env',
duplicate=0)
-
###################################################
#
# Let SCons do its thing. At this point SCons will use the defined
// been initialized
int maxThreadsPerCPU = 1;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
BaseCPU::BaseCPU(Params *p)
: SimObject(p->name), clock(p->clock), checkInterrupts(true),
params(p), number_of_threads(p->numberOfThreads), system(p->system)
p->max_loads_all_threads, *counter);
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
memset(interrupts, 0, sizeof(interrupts));
intstatus = 0;
#endif
{
for (int i = 0; i < execContexts.size(); ++i) {
ExecContext *xc = execContexts[i];
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
int id = params->cpu_id;
if (id != -1)
id += i;
newXC->takeOverFrom(oldXC);
assert(newXC->cpu_id == oldXC->cpu_id);
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
system->replaceExecContext(newXC, newXC->cpu_id);
#else
assert(newXC->process == oldXC->process);
#endif
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
for (int i = 0; i < NumInterruptLevels; ++i)
interrupts[i] = oldCPU->interrupts[i];
intstatus = oldCPU->intstatus;
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
void
BaseCPU::post_interrupt(int int_num, int index)
{
#include <vector>
#include "base/statistics.hh"
+#include "config/full_system.hh"
#include "cpu/sampler/sampler.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
#include "targetarch/isa_traits.hh"
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
class System;
#endif
inline Tick cycles(int numCycles) const { return clock * numCycles; }
inline Tick curCycle() const { return curTick / clock; }
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
protected:
uint64_t interrupts[NumInterruptLevels];
uint64_t intstatus;
Tick clock;
bool functionTrace;
Tick functionTraceStart;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
System *system;
int cpu_id;
#endif
*/
EventQueue **comLoadEventQueue;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
System *system;
/**
* Replace the disjoint functional memory with a unified one and remove
* this hack.
*/
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
req->paddr = req->vaddr;
#endif
#include "base/fast_alloc.hh"
#include "base/trace.hh"
+#include "config/full_system.hh"
#include "cpu/exetrace.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/comm.hh"
* Replace the disjoint functional memory with a unified one and remove
* this hack.
*/
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
req->paddr = req->vaddr;
#endif
* Replace the disjoint functional memory with a unified one and remove
* this hack.
*/
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
req->paddr = req->vaddr;
#endif
#include "cpu/base.hh"
#include "cpu/exec_context.hh"
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
#include "base/cprintf.hh"
#include "kern/kernel_stats.hh"
#include "sim/serialize.hh"
using namespace std;
// constructor
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
AlphaITB *_itb, AlphaDTB *_dtb,
FunctionalMemory *_mem)
ExecContext::~ExecContext()
{
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
delete kernelStats;
#endif
}
{
// some things should already be set up
assert(mem == oldContext->mem);
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
assert(system == oldContext->system);
#else
assert(process == oldContext->process);
oldContext->_status = ExecContext::Unallocated;
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
void
ExecContext::execute(const StaticInstBase *inst)
{
SERIALIZE_SCALAR(func_exe_inst);
SERIALIZE_SCALAR(inst);
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
kernelStats->serialize(os);
#endif
}
UNSERIALIZE_SCALAR(func_exe_inst);
UNSERIALIZE_SCALAR(inst);
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
kernelStats->unserialize(cp, section);
#endif
}
if (status() == Suspended)
return;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
// Don't change the status from active if there are pending interrupts
if (cpu->check_interrupts()) {
assert(status() == Active);
void
ExecContext::regStats(const string &name)
{
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
kernelStats->regStats(name + ".kern");
#endif
}
//TheISA::trap(fault); //One possible way to do it...
/** @todo: Going to hack it for now. Do a true fixup later. */
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
ev5_trap(fault);
#else
fatal("fault (%d) detected @ PC 0x%08p", fault, readPC());
#ifndef __CPU_EXEC_CONTEXT_HH__
#define __CPU_EXEC_CONTEXT_HH__
+#include "config/full_system.hh"
#include "mem/functional/functional.hh"
#include "mem/mem_req.hh"
#include "sim/host.hh"
class PhysicalMemory;
class BaseCPU;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
#include "sim/system.hh"
#include "targetarch/alpha_memory.hh"
// it belongs. For full-system mode, this is the system CPU ID.
int cpu_id;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
FunctionalMemory *mem;
AlphaITB *itb;
AlphaDTB *dtb;
unsigned storeCondFailures;
// constructor: initialize context from given process structure
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
#else
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string §ion);
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
bool validInstAddr(Addr addr) { return true; }
bool validDataAddr(Addr addr) { return true; }
int getInstAsid() { return regs.instAsid(); }
template <class T>
Fault read(MemReqPtr &req, T &data)
{
-#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
if (req->flags & LOCKED) {
MiscRegFile *cregs = &req->xc->regs.miscRegs;
cregs->lock_addr = req->paddr;
template <class T>
Fault write(MemReqPtr &req, T &data)
{
-#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
MiscRegFile *cregs;
regs.miscRegs.fpcr = val;
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault &fault);
Fault setIpr(int idx, uint64_t val);
int readIntrFlag() { return regs.intrflag; }
void trap(Fault fault);
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
IntReg getSyscallArg(int i)
{
return regs.intRegFile[ArgumentReg0 + i];
public:
AlphaFullCPU(Params ¶ms);
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
AlphaITB *itb;
AlphaDTB *dtb;
#endif
public:
void regStats();
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
//Note that the interrupt stuff from the base CPU might be somewhat
//ISA specific (ie NumInterruptLevels). These functions might not
//be needed in FullCPU though.
// Most of the full system code and syscall emulation is not yet
// implemented. These functions do show what the final interface will
// look like.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
uint64_t *getIpr();
uint64_t readIpr(int idx, Fault &fault);
Fault setIpr(int idx, uint64_t val);
#endif
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
// Need to change these into regfile calls that directly set a certain
// register. Actually, these functions should handle most of this
// functionality by themselves; should look up the rename and then
void copyFromXC();
public:
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
bool palShadowEnabled;
// Not sure this is used anywhere.
template <class T>
Fault read(MemReqPtr &req, T &data)
{
-#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
if (req->flags & LOCKED) {
MiscRegFile *cregs = &req->xc->regs.miscRegs;
cregs->lock_addr = req->paddr;
template <class T>
Fault write(MemReqPtr &req, T &data)
{
-#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
MiscRegFile *cregs;
#include "sim/sim_object.hh"
#include "sim/stats.hh"
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
#include "base/remote_gdb.hh"
#include "mem/functional/memory_control.hh"
#include "mem/functional/physical.hh"
Param<int> clock;
Param<int> numThreads;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
SimObjectParam<System *> system;
Param<int> cpu_id;
SimObjectParam<AlphaITB *> itb;
INIT_PARAM(clock, "clock speed"),
INIT_PARAM(numThreads, "number of HW thread contexts"),
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
INIT_PARAM(system, "System object"),
INIT_PARAM(cpu_id, "processor ID"),
INIT_PARAM(itb, "Instruction translation buffer"),
{
DerivAlphaFullCPU *cpu;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
// Full-system only supports a single thread for the moment.
int actual_num_threads = 1;
#else
params.name = getInstanceName();
params.numberOfThreads = actual_num_threads;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
params.system = system;
params.cpu_id = cpu_id;
params.itb = itb;
#include "cpu/o3/alpha_params.hh"
#include "cpu/o3/comm.hh"
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
#include "arch/alpha/osfpal.hh"
#include "arch/alpha/isa_traits.hh"
//#include "arch/alpha/ev5.hh"
this->commit.regStats();
}
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
// Will probably need to know which thread is calling syscall
// Will need to pass that information in to the DynInst when it is constructed,
this->funcExeInst = this->xc->func_exe_inst;
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
template <class Impl>
uint64_t *
uint64_t readFpcr();
void setFpcr(uint64_t val);
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault &fault);
Fault setIpr(int idx, uint64_t val);
Fault hwrei();
this->cpu->setFpcr(val);
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
template <class Impl>
uint64_t
AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
{
public:
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
AlphaITB *itb; AlphaDTB *dtb;
#else
std::vector<Process *> workload;
// in the IPR. Look at IPR[EXC_ADDR];
// hwrei() is what resets the PC to the place where instruction execution
// beings again.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
if (//checkInterrupts &&
cpu->check_interrupts() &&
!cpu->inPalMode(readCommitPC())) {
if (inst_fault != No_Fault && inst_fault != Fake_Mem_Fault) {
if (!head_inst->isNop()) {
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
cpu->trap(inst_fault);
#else // !FULL_SYSTEM
panic("fault (%d) detected @ PC %08p", inst_fault,
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifdef FULL_SYSTEM
+#include "config/full_system.hh"
+
+#if FULL_SYSTEM
#include "sim/system.hh"
#else
#include "sim/process.hh"
//Call constructor to all the pipeline stages here
template <class Impl>
FullO3CPU<Impl>::FullO3CPU(Params ¶ms)
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
: BaseFullCPU(params),
#else
: BaseFullCPU(params),
globalSeqNum(1),
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
system(params.system),
memCtrl(system->memctrl),
physmem(system->physmem),
{
_status = Idle;
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
thread.resize(this->number_of_threads);
#endif
for (int i = 0; i < this->number_of_threads; ++i) {
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
assert(i == 0);
system->execContexts[i] =
new ExecContext(this, i, system, itb, dtb, mem);
// Note that this is a hack so that my code which still uses xc-> will
// still work. I should remove this eventually
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
xc = system->execContexts[0];
#else
xc = thread[0];
// Need to do a copy of the xc->regs into the CPU's regfile so
// that it can start properly.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
ExecContext *src_xc = system->execContexts[0];
#else
ExecContext *src_xc = thread[0];
#include "base/statistics.hh"
#include "base/timebuf.hh"
+#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/cpu_policy.hh"
#include "cpu/exec_context.hh"
#include "sim/process.hh"
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
#include "arch/alpha/ev5.hh"
using namespace EV5;
#endif
public:
typedef BaseCPU::Params Params;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
BaseFullCPU(Params ¶ms);
#else
BaseFullCPU(Params ¶ms);
/** Get the current instruction sequence number, and increment it. */
InstSeqNum getAndIncrementInstSeq();
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
/** Check if this address is a valid instruction address. */
bool validInstAddr(Addr addr) { return true; }
/** Temporary function to get pointer to exec context. */
ExecContext *xcBase()
{
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
return system->execContexts[0];
#else
return thread[0];
InstSeqNum globalSeqNum;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
System *system;
MemoryController *memCtrl;
memReq = new MemReq();
// Not sure of this parameter. I think it should be based on the
// thread number.
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
memReq->asid = 0;
#else
memReq->asid = 0;
// of the instructions in the cache line until either the end of the
// cache line or a predicted taken branch is encountered.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
// Flag to say whether or not address is physical addr.
unsigned flags = cpu->inPalMode() ? PHYSICAL : 0;
#else
DPRINTF(Fetch, "Fetch: Blocked, need to handle the trap.\n");
_status = Blocked;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
// cpu->trap(fault);
// Send a signal to the ROB indicating that there's a trap from the
// fetch stage that needs to be handled. Need to indicate that
#include <queue>
+#include "config/full_system.hh"
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "cpu/o3/comm.hh"
LDSTQ ldstQueue;
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
public:
void lsqWriteback();
#endif
issueToExecQueue.advance();
}
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
template<class Impl>
void
SimpleIEW<Impl>::lsqWriteback()
#include "arch/alpha/isa_traits.hh"
#include "base/trace.hh"
+#include "config/full_system.hh"
#include "cpu/o3/comm.hh"
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
#include "arch/alpha/ev5.hh"
#include "kern/kernel_stats.hh"
miscRegs.fpcr = val;
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault &fault);
Fault setIpr(int idx, uint64_t val);
InternalProcReg *getIpr() { return ipr; }
/** Next-cycle program counter. */
Addr npc;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
private:
// This is ISA specifc stuff; remove it eventually once ISAImpl is used
IntReg palregs[NumIntRegs]; // PAL shadow registers
memset(floatRegFile, 0, sizeof(*floatRegFile));
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
//Problem: This code doesn't make sense at the RegFile level because it
//needs things such as the itb and dtb. Either put it at the CPU level or
return No_Fault;
}
-#endif // #ifdef FULL_SYSTEM
+#endif // #if FULL_SYSTEM
#endif // __CPU_O3_CPU_REGFILE_HH__
#include <list>
+#include "config/full_system.hh"
#include "cpu/o3/rename.hh"
template <class Impl>
InstSeqNum squashed_seq_num = fromCommit->commitInfo.doneSeqNum;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
assert(!historyBuffer.empty());
#else
// After a syscall squashes everything, the history buffer may be empty
// Ugly code, revamp all of the tick() functions eventually.
if (fromCommit->commitInfo.doneSeqNum != 0 && _status != Squashing) {
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
if (!fromCommit->commitInfo.squash) {
removeFromHistory(fromCommit->commitInfo.doneSeqNum);
}
#ifndef __CPU_O3_CPU_ROB_IMPL_HH__
#define __CPU_O3_CPU_ROB_IMPL_HH__
+#include "config/full_system.hh"
#include "cpu/o3/rob.hh"
template <class Impl>
// will never be false. Normally the squash would never be able
// to go past the head of the ROB; in this case it might, so it
// must be handled otherwise it will segfault.
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
if (squashIt == cpu->instList.begin()) {
DPRINTF(ROB, "ROB: Reached head of instruction list while "
"squashing.\n");
#define __CPU_OOO_CPU_OOO_CPU_HH__
#include "base/statistics.hh"
+#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/exec_context.hh"
#include "encumbered/cpu/full/fu_pool.hh"
#include "sim/eventq.hh"
// forward declarations
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
class Processor;
class AlphaITB;
class AlphaDTB;
MemInterface *icache_interface;
MemInterface *dcache_interface;
int width;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
AlphaITB *itb;
AlphaDTB *dtb;
FunctionalMemory *mem;
void switchOut();
void takeOverFrom(BaseCPU *oldCPU);
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
Addr dbg_vtophys(Addr addr);
bool interval_stats;
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string §ion);
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
bool validInstAddr(Addr addr) { return true; }
bool validDataAddr(Addr addr) { return true; }
int getInstAsid() { return xc->regs.instAsid(); }
DynInstPtr commitTable[ISA::TotalNumRegs];
// Might need a table of the shadow registers as well.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
DynInstPtr palShadowTable[ISA::NumIntRegs];
#endif
uint64_t readFpcr() { return xc->readFpcr(); }
void setFpcr(uint64_t val) { xc->setFpcr(val); }
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
Fault hwrei() { return xc->hwrei(); }
#include <utility>
#include "base/trace.hh"
+#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/exec_context.hh"
#include "cpu/pc_event.hh"
delete this;
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
extern "C"
void
sched_break_pc_sys(System *sys, Addr addr)
#include "sim/sim_object.hh"
#include "sim/stats.hh"
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
#include "base/remote_gdb.hh"
#include "mem/functional/memory_control.hh"
#include "mem/functional/physical.hh"
cacheCompletionEvent(this)
{
_status = Idle;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
// initialize CPU, including PC
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
Addr
SimpleCPU::dbg_vtophys(Addr addr)
{
}
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
void
SimpleCPU::post_interrupt(int int_num, int index)
{
Fault fault = No_Fault;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
if (checkInterrupts && check_interrupts() && !xc->inPalMode() &&
status() != IcacheMissComplete) {
int ipl = 0;
// Try to fetch an instruction
// set up memory request for instruction fetch
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
#else
#define IFETCH_FLAGS(pc) 0
traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst,
xc->regs.pc);
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
xc->setInst(inst);
#endif // FULL_SYSTEM
fault = curStaticInst->execute(this, traceData);
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
if (xc->fnbin)
xc->execute(curStaticInst.get());
#endif
} // if (fault == No_Fault)
if (fault != No_Fault) {
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
xc->ev5_trap(fault);
#else // !FULL_SYSTEM
fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
xc->regs.npc += sizeof(MachInst);
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
Addr oldpc;
do {
oldpc = xc->regs.pc;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDTB *> dtb;
SimObjectParam<FunctionalMemory *> mem;
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
INIT_PARAM(itb, "Instruction TLB"),
INIT_PARAM(dtb, "Data TLB"),
INIT_PARAM(mem, "memory"),
params->dcache_interface = (dcache) ? dcache->getInterface() : NULL;
params->width = width;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
params->itb = itb;
params->dtb = dtb;
params->mem = mem;
#define __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
#include "base/statistics.hh"
+#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/exec_context.hh"
#include "cpu/pc_event.hh"
#include "sim/eventq.hh"
// forward declarations
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
class Processor;
class AlphaITB;
class AlphaDTB;
MemInterface *icache_interface;
MemInterface *dcache_interface;
int width;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
AlphaITB *itb;
AlphaDTB *dtb;
FunctionalMemory *mem;
void switchOut(Sampler *s);
void takeOverFrom(BaseCPU *oldCPU);
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
Addr dbg_vtophys(Addr addr);
bool interval_stats;
uint64_t readFpcr() { return xc->readFpcr(); }
void setFpcr(uint64_t val) { xc->setFpcr(val); }
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
Fault hwrei() { return xc->hwrei(); }
f = file(str(target[0]), 'w')
print >>f, "import __main__"
print >>f, "__main__.m5_build_env = ",
- print >>f, scons_helper.flatten_defines(env['CPPDEFINES'])
+ print >>f, source[0]
f.close()
CFileCounter = 0
embedded_py_files.append(os.path.join(root, f))
embedfile_hh = os.path.join(env['SRCDIR'], 'base/embedfile.hh')
-env.Command('defines.py', None, MakeDefinesPyFile)
+
+optionDict = dict([(opt, env[opt]) for opt in env.ExportOptions])
+env.Command('defines.py', Value(optionDict), MakeDefinesPyFile)
+
env.Command('embedded_py.py', embedded_py_files, MakeEmbeddedPyFile)
env.Depends('embedded_py.cc', embedfile_hh)
env.Command('embedded_py.cc',
return result
+_bool_dict = {
+ 'true' : True, 't' : True, 'yes' : True, 'y' : True, '1' : True,
+ 'false' : False, 'f' : False, 'no' : False, 'n' : False, '0' : False
+ }
+
def toBool(value):
if not isinstance(value, str):
raise TypeError, "wrong type '%s' should be str" % type(value)
value = value.lower()
- if value == "true" or value == "t" or value == "yes" or value == "y":
- return True
- elif value == "false" or value == "f" or value == "no" or value == "n":
- return False
-
- raise ValueError, "cannot convert '%s' to bool" % value
+ result = _bool_dict.get(value, None)
+ if result == None:
+ raise ValueError, "cannot convert '%s' to bool" % value
+ return result
def toFrequency(value):
if not isinstance(value, str):
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
#include "base/statistics.hh"
+#include "config/full_system.hh"
#include "cpu/exec_context.hh"
#include "cpu/smt.hh"
#include "encumbered/cpu/full/thread.hh"
// when there's no OS: thus there's no resone to use it in FULL_SYSTEM
// mode when we do have an OS
//
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
#error "process.cc not compatible with FULL_SYSTEM"
#endif
// when there's no OS: thus there's no reason to use it in FULL_SYSTEM
// mode when we do have an OS.
//
-#ifndef FULL_SYSTEM
+#include "config/full_system.hh"
+
+#if !FULL_SYSTEM
#include <vector>
projects / gem5.git / commitdiff