update comments on sv.svstep

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index dfe3ce184ba207d5dc950c3789276fa93ae9a104..11994cf831011df1037999ec7839a1527557dc89 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -209,9 +209,9 @@ class SVP64Asm:
             yield ".long 0x%x" % insn
             return
 
-        # this is a *32-bit-only* instruction. it updates SVSTATE.
-        # it is *not* a 64-bit-prefixed Vector instruction (no sv.svstep),
-        # it is a Vector *control* instruction.
+        # this is a 32-bit instruction. it updates SVSTATE.
+        # it *can* be SVP64-prefixed, to indicate that its registers
+        # are Vectorised.
         # note: EXT022 is the "sandbox" major opcode so it's fine to add
 
         # sigh have to do setvl here manually for now...