radeonsi: Enable tiling for depth/stencil resources.

Enabling it for all resources still seems to cause problems, but depth/stencil
buffers are always accessed with tiling by the DB block.

Also, stick to 1D tiling for now. Getting 2D tiling to work properly will
require substantial changes in libdrm_radeon and possibly the kernel as well.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>

diff --git a/src/gallium/drivers/radeonsi/r600_texture.c b/src/gallium/drivers/radeonsi/r600_texture.c
index de46640d7e495741f5e5468ff52bc90a8de78e9e..580af540f7457e73bfee048e71e45bf0654c4965 100644 (file)
--- a/src/gallium/drivers/radeonsi/r600_texture.c
+++ b/src/gallium/drivers/radeonsi/r600_texture.c
@@ -521,14 +521,13 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
        unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
        int r;
 
-#if 0
        if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
-           !(templ->bind & PIPE_BIND_SCANOUT)) {
+           !(templ->bind & PIPE_BIND_SCANOUT) &&
+           util_format_is_depth_or_stencil(templ->format)) {
                if (permit_hardware_blit(screen, templ)) {
-                       array_mode = V_009910_ARRAY_2D_TILED_THIN1;
+                       array_mode = V_009910_ARRAY_1D_TILED_THIN1;
                }
        }
-#endif
 
        r = r600_init_surface(rscreen, &surface, templ, array_mode,
                              templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);