ruby: Fix MOESI_hammer cache profiler calls for L2 misses

diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
index 4bdfcb23d17edd5ba8def37c2d5c7e506817109d..10a14e2e7496b3179c2d5743725acd0719d66270 100644 (file)
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -683,7 +683,8 @@ machine(L1Cache, "AMD Hammer-like protocol")
         L1IcacheMemory.profileMiss(in_msg);
       } else if (L1DcacheMemory.isTagPresent(address)) {
         L1DcacheMemory.profileMiss(in_msg);
-      } else {
+      }
+      if (L2cacheMemory.isTagPresent(address) == false) {
         L2cacheMemory.profileMiss(in_msg);
       }
     }
@@ -724,12 +725,14 @@ machine(L1Cache, "AMD Hammer-like protocol")
   transition({I, S, O, M, MM}, L2_to_L1D) {
     ii_allocateL1DCacheBlock;
     tt_copyFromL2toL1; // Not really needed for state I
+    uu_profileMiss;
     rr_deallocateL2CacheBlock;
   }
 
   transition({I, S, O, M, MM}, L2_to_L1I) {
     jj_allocateL1ICacheBlock;
     tt_copyFromL2toL1; // Not really needed for state I
+    uu_profileMiss;
     rr_deallocateL2CacheBlock;
   }