* config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
(print_operand) ['U']: Likewise.
(alpha_expand_unaligned_store): Correct constants for 32-bit cross.
(alpha_expand_unaligned_store_words): Likewise.
(alpha_expand_builtin_vector_binop): Fix typo.
(enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
umulh, and cix insns.
(one_arg_builtins): Add cix builtins.
(two_arg_builtins): Add ext, ins, msk, umulh builtins.
(alpha_expand_builtin): Fix typo in arity.
* config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
(builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
builtin_ctlz, builtin_ctpop): New.
* doc/extend.texi (Alpha Built-in Functions): Update.
* gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
* gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
* gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
From-SVN: r54267
+2002-06-04 Richard Henderson <rth@redhat.com>
+
+ * config/alpha/alpha.c (mode_mask_operand): Simplify without ifdefs.
+ (print_operand) ['U']: Likewise.
+ (alpha_expand_unaligned_store): Correct constants for 32-bit cross.
+ (alpha_expand_unaligned_store_words): Likewise.
+ (alpha_expand_builtin_vector_binop): Fix typo.
+ (enum alpha_builtin, code_for_builtin): Add remaining ext, ins, msk,
+ umulh, and cix insns.
+ (one_arg_builtins): Add cix builtins.
+ (two_arg_builtins): Add ext, ins, msk, umulh builtins.
+ (alpha_expand_builtin): Fix typo in arity.
+ * config/alpha/alpha.md (UNSPEC_CTLZ, UNSPEC_CTPOP): New.
+ (builtin_extbl, builtin_extwl, builtin_extll, builtin_extwh,
+ builtin_extlh, builtin_insbl, builtin_inswl, builtin_insll,
+ builtin_insql, builtin_inswh, builtin_inslh, builtin_insqh,
+ builtin_mskbl, builtin_mskwl, builtin_mskll, builtin_mskql,
+ builtin_mskwh, builtin_msklh, builtin_mskqh, builtin_cttz,
+ builtin_ctlz, builtin_ctpop): New.
+ * doc/extend.texi (Alpha Built-in Functions): Update.
+
2002-06-04 Geoffrey Keating <geoffk@redhat.com>
* gengtype.c (write_gc_root): Don't unnecessarily prevent
register rtx op;
enum machine_mode mode ATTRIBUTE_UNUSED;
{
-#if HOST_BITS_PER_WIDE_INT == 32
- if (GET_CODE (op) == CONST_DOUBLE)
- return (CONST_DOUBLE_LOW (op) == -1
- && (CONST_DOUBLE_HIGH (op) == -1
- || CONST_DOUBLE_HIGH (op) == 0));
-#else
- if (GET_CODE (op) == CONST_DOUBLE)
- return (CONST_DOUBLE_LOW (op) == -1 && CONST_DOUBLE_HIGH (op) == 0);
-#endif
+ if (GET_CODE (op) == CONST_INT)
+ {
+ HOST_WIDE_INT value = INTVAL (op);
- return (GET_CODE (op) == CONST_INT
- && (INTVAL (op) == 0xff
- || INTVAL (op) == 0xffff
- || INTVAL (op) == (HOST_WIDE_INT)0xffffffff
-#if HOST_BITS_PER_WIDE_INT == 64
- || INTVAL (op) == -1
-#endif
- ));
+ if (value == 0xff)
+ return 1;
+ if (value == 0xffff)
+ return 1;
+ if (value == 0xffffffff)
+ return 1;
+ if (value == -1)
+ return 1;
+ }
+ else if (HOST_BITS_PER_WIDE_INT == 32 && GET_CODE (op) == CONST_DOUBLE)
+ {
+ if (CONST_DOUBLE_LOW (op) == 0xffffffff && CONST_DOUBLE_HIGH (op) == 0)
+ return 1;
+ }
+
+ return 0;
}
/* Return 1 if OP is a multiple of 8 less than 64. */
emit_insn (gen_mskxl_be (dsth, dsth, GEN_INT (0xffff), addr));
break;
case 4:
- emit_insn (gen_mskxl_be (dsth, dsth, GEN_INT (0xffffffff), addr));
- break;
- case 8:
{
-#if HOST_BITS_PER_WIDE_INT == 32
- rtx msk = immed_double_const (0xffffffff, 0xffffffff, DImode);
-#else
- rtx msk = constm1_rtx;
-#endif
+ rtx msk = immed_double_const (0xffffffff, 0, DImode);
emit_insn (gen_mskxl_be (dsth, dsth, msk, addr));
+ break;
}
+ case 8:
+ emit_insn (gen_mskxl_be (dsth, dsth, constm1_rtx, addr));
break;
}
emit_insn (gen_mskxl_le (dstl, dstl, GEN_INT (0xffff), addr));
break;
case 4:
- emit_insn (gen_mskxl_le (dstl, dstl, GEN_INT (0xffffffff), addr));
- break;
- case 8:
{
-#if HOST_BITS_PER_WIDE_INT == 32
- rtx msk = immed_double_const (0xffffffff, 0xffffffff, DImode);
-#else
- rtx msk = constm1_rtx;
-#endif
+ rtx msk = immed_double_const (0xffffffff, 0, DImode);
emit_insn (gen_mskxl_le (dstl, dstl, msk, addr));
+ break;
}
+ case 8:
+ emit_insn (gen_mskxl_le (dstl, dstl, constm1_rtx, addr));
break;
}
}
{
rtx const im8 = GEN_INT (-8);
rtx const i64 = GEN_INT (64);
-#if HOST_BITS_PER_WIDE_INT == 32
- rtx const im1 = immed_double_const (0xffffffff, 0xffffffff, DImode);
-#else
- rtx const im1 = constm1_rtx;
-#endif
rtx ins_tmps[MAX_MOVE_WORDS];
rtx st_tmp_1, st_tmp_2, dreg;
rtx st_addr_1, st_addr_2, dmema;
/* Split and merge the ends with the destination data. */
if (WORDS_BIG_ENDIAN)
{
- emit_insn (gen_mskxl_be (st_tmp_2, st_tmp_2, im1, dreg));
+ emit_insn (gen_mskxl_be (st_tmp_2, st_tmp_2, constm1_rtx, dreg));
emit_insn (gen_mskxh (st_tmp_1, st_tmp_1, i64, dreg));
}
else
{
emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg));
- emit_insn (gen_mskxl_le (st_tmp_1, st_tmp_1, im1, dreg));
+ emit_insn (gen_mskxl_le (st_tmp_1, st_tmp_1, constm1_rtx, dreg));
}
if (data_regs != NULL)
op1 = CONST0_RTX (mode);
else
op1 = gen_lowpart (mode, op1);
- if (op1 == const0_rtx)
+
+ if (op2 == const0_rtx)
op2 = CONST0_RTX (mode);
else
op2 = gen_lowpart (mode, op2);
case 'U':
/* Similar, except do it from the mask. */
- if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xff)
- fprintf (file, "b");
- else if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xffff)
- fprintf (file, "w");
- else if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xffffffff)
- fprintf (file, "l");
-#if HOST_BITS_PER_WIDE_INT == 32
- else if (GET_CODE (x) == CONST_DOUBLE
- && CONST_DOUBLE_HIGH (x) == 0
- && CONST_DOUBLE_LOW (x) == -1)
- fprintf (file, "l");
- else if (GET_CODE (x) == CONST_DOUBLE
- && CONST_DOUBLE_HIGH (x) == -1
- && CONST_DOUBLE_LOW (x) == -1)
- fprintf (file, "q");
-#else
- else if (GET_CODE (x) == CONST_INT && INTVAL (x) == -1)
- fprintf (file, "q");
- else if (GET_CODE (x) == CONST_DOUBLE
- && CONST_DOUBLE_HIGH (x) == 0
- && CONST_DOUBLE_LOW (x) == -1)
- fprintf (file, "q");
-#endif
- else
- output_operand_lossage ("invalid %%U value");
+ if (GET_CODE (x) == CONST_INT)
+ {
+ HOST_WIDE_INT value = INTVAL (x);
+
+ if (value == 0xff)
+ {
+ fputc ('b', file);
+ break;
+ }
+ if (value == 0xffff)
+ {
+ fputc ('w', file);
+ break;
+ }
+ if (value == 0xffffffff)
+ {
+ fputc ('l', file);
+ break;
+ }
+ if (value == -1)
+ {
+ fputc ('q', file);
+ break;
+ }
+ }
+ else if (HOST_BITS_PER_WIDE_INT == 32
+ && GET_CODE (x) == CONST_DOUBLE
+ && CONST_DOUBLE_LOW (x) == 0xffffffff
+ && CONST_DOUBLE_HIGH (x) == 0)
+ {
+ fputc ('l', file);
+ break;
+ }
+ output_operand_lossage ("invalid %%U value");
break;
case 's':
enum alpha_builtin
{
ALPHA_BUILTIN_CMPBGE,
+ ALPHA_BUILTIN_EXTBL,
+ ALPHA_BUILTIN_EXTWL,
+ ALPHA_BUILTIN_EXTLL,
ALPHA_BUILTIN_EXTQL,
+ ALPHA_BUILTIN_EXTWH,
+ ALPHA_BUILTIN_EXTLH,
ALPHA_BUILTIN_EXTQH,
+ ALPHA_BUILTIN_INSBL,
+ ALPHA_BUILTIN_INSWL,
+ ALPHA_BUILTIN_INSLL,
+ ALPHA_BUILTIN_INSQL,
+ ALPHA_BUILTIN_INSWH,
+ ALPHA_BUILTIN_INSLH,
+ ALPHA_BUILTIN_INSQH,
+ ALPHA_BUILTIN_MSKBL,
+ ALPHA_BUILTIN_MSKWL,
+ ALPHA_BUILTIN_MSKLL,
+ ALPHA_BUILTIN_MSKQL,
+ ALPHA_BUILTIN_MSKWH,
+ ALPHA_BUILTIN_MSKLH,
+ ALPHA_BUILTIN_MSKQH,
+ ALPHA_BUILTIN_UMULH,
ALPHA_BUILTIN_ZAP,
ALPHA_BUILTIN_ZAPNOT,
ALPHA_BUILTIN_AMASK,
ALPHA_BUILTIN_UNPKBL,
ALPHA_BUILTIN_UNPKBW,
+ /* TARGET_CIX */
+ ALPHA_BUILTIN_CTTZ,
+ ALPHA_BUILTIN_CTLZ,
+ ALPHA_BUILTIN_CTPOP,
+
ALPHA_BUILTIN_max
};
+static unsigned int const code_for_builtin[ALPHA_BUILTIN_max] = {
+ CODE_FOR_builtin_cmpbge,
+ CODE_FOR_builtin_extbl,
+ CODE_FOR_builtin_extwl,
+ CODE_FOR_builtin_extll,
+ CODE_FOR_builtin_extql,
+ CODE_FOR_builtin_extwh,
+ CODE_FOR_builtin_extlh,
+ CODE_FOR_builtin_extqh,
+ CODE_FOR_builtin_insbl,
+ CODE_FOR_builtin_inswl,
+ CODE_FOR_builtin_insll,
+ CODE_FOR_builtin_insql,
+ CODE_FOR_builtin_inswh,
+ CODE_FOR_builtin_inslh,
+ CODE_FOR_builtin_insqh,
+ CODE_FOR_builtin_mskbl,
+ CODE_FOR_builtin_mskwl,
+ CODE_FOR_builtin_mskll,
+ CODE_FOR_builtin_mskql,
+ CODE_FOR_builtin_mskwh,
+ CODE_FOR_builtin_msklh,
+ CODE_FOR_builtin_mskqh,
+ CODE_FOR_umuldi3_highpart,
+ CODE_FOR_builtin_zap,
+ CODE_FOR_builtin_zapnot,
+ CODE_FOR_builtin_amask,
+ CODE_FOR_builtin_implver,
+ CODE_FOR_builtin_rpcc,
+
+ /* TARGET_MAX */
+ CODE_FOR_builtin_minub8,
+ CODE_FOR_builtin_minsb8,
+ CODE_FOR_builtin_minuw4,
+ CODE_FOR_builtin_minsw4,
+ CODE_FOR_builtin_maxub8,
+ CODE_FOR_builtin_maxsb8,
+ CODE_FOR_builtin_maxuw4,
+ CODE_FOR_builtin_maxsw4,
+ CODE_FOR_builtin_perr,
+ CODE_FOR_builtin_pklb,
+ CODE_FOR_builtin_pkwb,
+ CODE_FOR_builtin_unpkbl,
+ CODE_FOR_builtin_unpkbw,
+
+ /* TARGET_CIX */
+ CODE_FOR_builtin_cttz,
+ CODE_FOR_builtin_ctlz,
+ CODE_FOR_builtin_ctpop
+};
+
struct alpha_builtin_def
{
const char *name;
{ "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB, MASK_MAX },
{ "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB, MASK_MAX },
{ "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL, MASK_MAX },
- { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW, MASK_MAX }
+ { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW, MASK_MAX },
+ { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ, MASK_CIX },
+ { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ, MASK_CIX },
+ { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP, MASK_CIX }
};
static struct alpha_builtin_def const two_arg_builtins[] = {
{ "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE, 0 },
+ { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL, 0 },
+ { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL, 0 },
+ { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL, 0 },
{ "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL, 0 },
+ { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH, 0 },
+ { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH, 0 },
{ "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH, 0 },
+ { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL, 0 },
+ { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL, 0 },
+ { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL, 0 },
+ { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL, 0 },
+ { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH, 0 },
+ { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH, 0 },
+ { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH, 0 },
+ { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL, 0 },
+ { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL, 0 },
+ { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL, 0 },
+ { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL, 0 },
+ { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH, 0 },
+ { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH, 0 },
+ { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH, 0 },
+ { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH, 0 },
{ "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP, 0 },
{ "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT, 0 },
{ "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8, MASK_MAX },
enum machine_mode mode ATTRIBUTE_UNUSED;
int ignore ATTRIBUTE_UNUSED;
{
- static unsigned int const code_for_builtin[ALPHA_BUILTIN_max] = {
- CODE_FOR_builtin_cmpbge,
- CODE_FOR_builtin_extql,
- CODE_FOR_builtin_extqh,
- CODE_FOR_builtin_zap,
- CODE_FOR_builtin_zapnot,
- CODE_FOR_builtin_amask,
- CODE_FOR_builtin_implver,
- CODE_FOR_builtin_rpcc,
- CODE_FOR_builtin_minub8,
- CODE_FOR_builtin_minsb8,
- CODE_FOR_builtin_minuw4,
- CODE_FOR_builtin_minsw4,
- CODE_FOR_builtin_maxub8,
- CODE_FOR_builtin_maxsb8,
- CODE_FOR_builtin_maxuw4,
- CODE_FOR_builtin_maxsw4,
- CODE_FOR_builtin_perr,
- CODE_FOR_builtin_pklb,
- CODE_FOR_builtin_pkwb,
- CODE_FOR_builtin_unpkbl,
- CODE_FOR_builtin_unpkbw,
- };
-
#define MAX_ARGS 2
tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
op[arity] = expand_expr (arg, NULL_RTX, VOIDmode, 0);
- insn_op = &insn_data[icode].operand[arity];
+ insn_op = &insn_data[icode].operand[arity + 1];
if (!(*insn_op->predicate) (op[arity], insn_op->mode))
op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
}
(UNSPEC_AMASK 24)
(UNSPEC_IMPLVER 25)
(UNSPEC_PERR 26)
+ (UNSPEC_CTLZ 27)
+ (UNSPEC_CTPOP 28)
])
;; UNSPEC_VOLATILE:
;; actually differentiate between ILOG and ICMP in the schedule.
[(set_attr "type" "icmp")])
+(define_expand "builtin_extbl"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_extxl_be;
+ else
+ gen = gen_extxl_le;
+ emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_extwl"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_extxl_be;
+ else
+ gen = gen_extxl_le;
+ emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_extll"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_extxl_be;
+ else
+ gen = gen_extxl_le;
+ emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
+ DONE;
+})
+
(define_expand "builtin_extql"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
DONE;
})
+(define_expand "builtin_extwh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_extwh_be;
+ else
+ gen = gen_extwh_le;
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_extlh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_extlh_be;
+ else
+ gen = gen_extlh_le;
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
(define_expand "builtin_extqh"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
DONE;
})
+(define_expand "builtin_insbl"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_insbl_be;
+ else
+ gen = gen_insbl_le;
+ operands[1] = gen_lowpart (QImode, operands[1]);
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_inswl"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_inswl_be;
+ else
+ gen = gen_inswl_le;
+ operands[1] = gen_lowpart (HImode, operands[1]);
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_insll"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_insll_be;
+ else
+ gen = gen_insll_le;
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_insql"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_insql_be;
+ else
+ gen = gen_insql_le;
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_inswh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_inslh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_insqh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_mskbl"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ rtx mask;
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_mskxl_be;
+ else
+ gen = gen_mskxl_le;
+ mask = GEN_INT (0xff);
+ emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_mskwl"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ rtx mask;
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_mskxl_be;
+ else
+ gen = gen_mskxl_le;
+ mask = GEN_INT (0xffff);
+ emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_mskll"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ rtx mask;
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_mskxl_be;
+ else
+ gen = gen_mskxl_le;
+ mask = immed_double_const (0xffffffff, 0, DImode);
+ emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_mskql"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ rtx mask;
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_mskxl_be;
+ else
+ gen = gen_mskxl_le;
+ mask = constm1_rtx;
+ emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_mskwh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_msklh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_mskqh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
+ DONE;
+})
+
(define_expand "builtin_zap"
[(set (match_operand:DI 0 "register_operand" "")
(and:DI (unspec:DI
"TARGET_MAX"
"unpkbw %r1,%0"
[(set_attr "type" "mvi")])
+
+(define_expand "builtin_cttz"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "")]
+ UNSPEC_CTTZ))]
+ "TARGET_CIX"
+ "")
+
+(define_insn "builtin_ctlz"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+ UNSPEC_CTLZ))]
+ "TARGET_CIX"
+ "ctlz %1,%0"
+ [(set_attr "type" "mvi")])
+
+(define_insn "builtin_ctpop"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+ UNSPEC_CTPOP))]
+ "TARGET_CIX"
+ "ctpop %1,%0"
+ [(set_attr "type" "mvi")])
\f
;; The call patterns are at the end of the file because their
;; wildcard operand0 interferes with nice recognition.
long __builtin_alpha_rpcc (void)
long __builtin_alpha_amask (long)
long __builtin_alpha_cmpbge (long, long)
+long __builtin_alpha_extbl (long, long)
+long __builtin_alpha_extwl (long, long)
+long __builtin_alpha_extll (long, long)
long __builtin_alpha_extql (long, long)
+long __builtin_alpha_extwh (long, long)
+long __builtin_alpha_extlh (long, long)
long __builtin_alpha_extqh (long, long)
+long __builtin_alpha_insbl (long, long)
+long __builtin_alpha_inswl (long, long)
+long __builtin_alpha_insll (long, long)
+long __builtin_alpha_insql (long, long)
+long __builtin_alpha_inswh (long, long)
+long __builtin_alpha_inslh (long, long)
+long __builtin_alpha_insqh (long, long)
+long __builtin_alpha_mskbl (long, long)
+long __builtin_alpha_mskwl (long, long)
+long __builtin_alpha_mskll (long, long)
+long __builtin_alpha_mskql (long, long)
+long __builtin_alpha_mskwh (long, long)
+long __builtin_alpha_msklh (long, long)
+long __builtin_alpha_mskqh (long, long)
+long __builtin_alpha_umulh (long, long)
long __builtin_alpha_zap (long, long)
long __builtin_alpha_zapnot (long, long)
@end example
long __builtin_alpha_perr (long, long)
@end example
+The following built-in functions are always with @option{-mcix}
+or @option{-mcpu=@var{cpu}} where @var{cpu} is @code{ev67} or
+later. They all generate the machine instruction that is part
+of the name.
+
+@example
+long __builtin_alpha_cttz (long)
+long __builtin_alpha_ctlz (long)
+long __builtin_alpha_ctpop (long)
+@end example
+
@node X86 Built-in Functions
@subsection X86 Built-in Functions
+2002-06-04 Richard Henderson <rth@redhat.com>
+
+ * gcc.dg/alpha-base-1.c: Add ext/ins/msk/umulh cases.
+ * gcc.dg/alpha-max-1.c, gcc.dg/alpha-max-2.c: Use -mcpu=ev67.
+ * gcc.dg/alpha-cix-1.c, gcc.dg/alpha-cix-2.c: New.
+
2002-06-04 Aldy Hernandez <aldyh@redhat.com>
* gcc.dg/altivec-2.c: Remove test for invalid vector type V2DF.
sink = __builtin_alpha_cmpbge (x, y);
sink = __builtin_alpha_cmpbge (-1, x);
+
+ sink = __builtin_alpha_extbl (x, y);
+ sink = __builtin_alpha_extwl (x, y);
+ sink = __builtin_alpha_extll (x, y);
sink = __builtin_alpha_extql (x, y);
+ sink = __builtin_alpha_extwh (x, y);
+ sink = __builtin_alpha_extlh (x, y);
sink = __builtin_alpha_extqh (x, y);
+
+ sink = __builtin_alpha_insbl (x, y);
+ sink = __builtin_alpha_inswl (x, y);
+ sink = __builtin_alpha_insll (x, y);
+ sink = __builtin_alpha_insql (x, y);
+ sink = __builtin_alpha_inswh (x, y);
+ sink = __builtin_alpha_inslh (x, y);
+ sink = __builtin_alpha_insqh (x, y);
+
+ sink = __builtin_alpha_mskbl (x, y);
+ sink = __builtin_alpha_mskwl (x, y);
+ sink = __builtin_alpha_mskll (x, y);
+ sink = __builtin_alpha_mskql (x, y);
+ sink = __builtin_alpha_mskwh (x, y);
+ sink = __builtin_alpha_msklh (x, y);
+ sink = __builtin_alpha_mskqh (x, y);
+
+ sink = __builtin_alpha_umulh (x, y);
}
void test_zap (long x, long y)
--- /dev/null
+/* Test that the CIX isa builtins compile. */
+/* { dg-do link { target alpha*-*-* } } */
+/* { dg-options "-mcpu=ev67" } */
+
+void test_CIX (long x)
+{
+ volatile long sink;
+
+ sink = __builtin_alpha_cttz (x);
+ sink = __builtin_alpha_ctlz (x);
+ sink = __builtin_alpha_ctpop (x);
+}
+
+int main() { return 0; }
--- /dev/null
+/* Test that alpha-cix-1.c compiles with optimization. */
+/* { dg-do link { target alpha*-*-* } } */
+/* { dg-options "-mcpu=ev67 -O2" } */
+
+#include "alpha-cix-1.c"
/* Test that the MAX isa builtins compile. */
/* { dg-do link { target alpha*-*-* } } */
-/* { dg-options "-mmax" } */
+/* { dg-options "-mcpu=pca56" } */
void test_MAX (long x, long y)
{
/* Test that alpha-max-1.c compiles with optimization. */
/* { dg-do link { target alpha*-*-* } } */
-/* { dg-options "-mmax -O2" } */
+/* { dg-options "-mcpu=pca56 -O2" } */
#include "alpha-max-1.c"
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