78: 0789 ffcf b 0 <text_label>
7c: 0785 ffef b.d 0 <text_label>
80: 264a 7000 mov 0,0
- 84: 077c ffe1 b.deq -132
+ 84: 077c ffe1 beq.d -132
88: 264a 7000 mov 0,0
8c: 0774 ffc2 bne -140
- 90: 0770 ffe6 b.dnc -144
+ 90: 0770 ffe6 bnc.d -144
94: 264a 7000 mov 0,0
+2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
+ instructions.
+
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
{ "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM25_A16_5 }, { C_D }},
/* b<.d><cc> s21 00000ssssssssss0SSSSSSSSSSNQQQQQ. */
-{ "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM21_A16_5 }, { C_D, C_CC }},
+{ "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM21_A16_5 }, { C_CC, C_D }},
/* bbit0<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01110. */
{ "bbit0", 0x0801000E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},