vc707mig: use an external ibuf

This makes it possible to also drive a PLL of our own from the crystal.

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index 58d14f4de44c3a28234abf15d54ebb222a04a7d5..f6ae153107a4ff9558056f54c3703004baab7643 100644 (file)
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@ -77,9 +77,8 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
     io.port.ddr3_odt          := blackbox.io.ddr3_odt
 
     //inputs
-    //differential system clock
-    blackbox.io.sys_clk_n     := io.port.sys_clk_n
-    blackbox.io.sys_clk_p     := io.port.sys_clk_p
+    //NO_BUFFER clock
+    blackbox.io.sys_clk_i     := io.port.sys_clk_i
 
     //user interface signals
     val axi_async = axi4.bundleIn(0)

diff --git a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
index 6f281ecbaea0ce9d9015a8ac7a42f9913fc37dd3..d7b522fd7eaa0ab38c7a67638387353fe60ddeb5 100644 (file)
--- a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
+++ b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
@@ -31,9 +31,8 @@ trait VC707MIGIODDR extends Bundle {
 //reused directly in io bundle for sifive.blocks.devices.xilinxvc707mig
 trait VC707MIGIOClocksReset extends Bundle {
   //inputs
-  //differential system clocks
-  val sys_clk_n             = Bool(INPUT)
-  val sys_clk_p             = Bool(INPUT)
+  //"NO_BUFFER" clock source (must be connected to IBUF outside of IP)
+  val sys_clk_i             = Bool(INPUT)
   //user interface signals
   val ui_clk                = Clock(OUTPUT)
   val ui_clk_sync_rst       = Bool(OUTPUT)