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diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn
index 45b1a8d829b4ac0cd656d8c1e85e361922a17581..2f5d5b58a9deeb44967052e045584199e59c90f6 100644 (file)
--- a/docs/pinmux.mdwn
+++ b/docs/pinmux.mdwn
@@ -28,11 +28,11 @@ at very low frequencies (5 khz is perfectly acceptable)
 so there is very little risk of clock skew during that testing.
 
 Additionally, an SoC is designed to be low cost, to use low cost
-packaging. ASICs are typically 32 to 128 pins QFP
-only in the Embedded
+packaging. ASICs are typically only 32 to 128 pins QFP
+in the Embedded
 Controller range, and between 300 to 650 FBGA in the Tablet /
 Smartphone range, absolute maximum of 19 mm on a side.
-1,000 pin packages common to Intel desktop processors are
+2 to 3 in square 1,000 pin packages common to Intel desktop processors are
 absolutely out of the question.
 
 (*With each pin wire bond smashing