targets/kc705: use DDRPHY_CMD_DELAY to center write leveling.

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 67cdf274c1d335674648b287663b916905155eab..874f39ab05368bcdda6d5894a170211fbda8b2d7 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -57,8 +57,10 @@ class BaseSoC(SoCSDRAM):
             self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
                 memtype      = "DDR3",
                 nphases      = 4,
-                sys_clk_freq = sys_clk_freq)
+                sys_clk_freq = sys_clk_freq,
+                cmd_latency  = 1)
             self.add_csr("ddrphy")
+            self.add_constant("DDRPHY_CMD_DELAY", 13)
             sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
             self.register_sdram(self.ddrphy,
                 geom_settings   = sdram_module.geom_settings,