entry->start = (backend_instruction *) instructions->get_head();
- foreach_list(node, instructions) {
- backend_instruction *inst = (backend_instruction *)node;
-
+ foreach_in_list(backend_instruction, inst, instructions) {
cur->end = inst;
/* set_next_block wants the post-incremented ip */
prog_data->curb_read_length = ALIGN(stage_prog_data->nr_params, 8) / 8;
/* Map the offsets in the UNIFORM file to fixed HW regs. */
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *)node;
-
+ foreach_in_list(fs_inst, inst, &instructions) {
for (unsigned int i = 0; i < inst->sources; i++) {
if (inst->src[i].file == UNIFORM) {
int uniform_nr = inst->src[i].reg + inst->src[i].reg_offset;
/* Offset all the urb_setup[] index by the actual position of the
* setup regs, now that the location of the constants has been chosen.
*/
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *)node;
-
+ foreach_in_list(fs_inst, inst, &instructions) {
if (inst->opcode == FS_OPCODE_LINTERP) {
assert(inst->src[2].file == HW_REG);
inst->src[2].fixed_hw_reg.nr += urb_start;
false;
}
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *)node;
-
+ foreach_in_list(fs_inst, inst, &instructions) {
/* If there's a SEND message that requires contiguous destination
* registers, no splitting is allowed.
*/
}
}
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *)node;
-
+ foreach_in_list(fs_inst, inst, &instructions) {
if (inst->dst.file == GRF &&
split_grf[inst->dst.reg] &&
inst->dst.reg_offset != 0) {
int remap_table[this->virtual_grf_count];
memset(remap_table, -1, sizeof(remap_table));
- foreach_list(node, &this->instructions) {
- const fs_inst *inst = (const fs_inst *) node;
-
+ foreach_in_list(const fs_inst, inst, &instructions) {
if (inst->dst.file == GRF)
remap_table[inst->dst.reg] = 0;
this->virtual_grf_count = new_index;
/* Patch all the instructions to use the newly renumbered registers */
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *) node;
-
+ foreach_in_list(fs_inst, inst, &instructions) {
if (inst->dst.file == GRF)
inst->dst.reg = remap_table[inst->dst.reg];
is_live[i] = false;
}
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *) node;
-
+ foreach_in_list(fs_inst, inst, &instructions) {
for (int i = 0; i < inst->sources; i++) {
if (inst->src[i].file != UNIFORM)
continue;
void
fs_visitor::demote_pull_constants()
{
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *)node;
-
+ foreach_in_list(fs_inst, inst, &instructions) {
for (int i = 0; i < inst->sources; i++) {
if (inst->src[i].file != UNIFORM)
continue;
{
bool progress = false;
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *)node;
-
+ foreach_in_list(fs_inst, inst, &instructions) {
switch (inst->opcode) {
case BRW_OPCODE_MUL:
if (inst->src[1].file != IMM)
void
fs_visitor::lower_uniform_pull_constant_loads()
{
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *)node;
-
+ foreach_in_list(fs_inst, inst, &instructions) {
if (inst->opcode != FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD)
continue;
}
int ip = 0, max_pressure = 0;
- foreach_list(node, &this->instructions) {
- backend_instruction *inst = (backend_instruction *)node;
+ foreach_in_list(backend_instruction, inst, &instructions) {
max_pressure = MAX2(max_pressure, regs_live_at_ip[ip]);
fprintf(file, "{%3d} %4d: ", regs_live_at_ip[ip], ip);
dump_instruction(inst, file);
calculate_live_intervals();
int num_instructions = 0;
- foreach_list(node, &this->instructions) {
+ foreach_in_list(fs_inst, inst, &instructions) {
++num_instructions;
}
* functions called "main").
*/
if (shader) {
- foreach_list(node, &*shader->base.ir) {
- ir_instruction *ir = (ir_instruction *)node;
+ foreach_in_list(ir_instruction, ir, shader->base.ir) {
base_ir = ir;
this->result = reg_undef;
ir->accept(this);
num_acp = 0;
for (int b = 0; b < cfg->num_blocks; b++) {
for (int i = 0; i < ACP_HASH_SIZE; i++) {
- foreach_list(entry_node, &out_acp[b][i]) {
+ foreach_in_list(acp_entry, entry, &out_acp[b][i]) {
num_acp++;
}
}
bd[b].kill = rzalloc_array(bd, BITSET_WORD, bitset_words);
for (int i = 0; i < ACP_HASH_SIZE; i++) {
- foreach_list(entry_node, &out_acp[b][i]) {
- acp_entry *entry = (acp_entry *)entry_node;
-
+ foreach_in_list(acp_entry, entry, &out_acp[b][i]) {
acp[next_acp] = entry;
/* opt_copy_propagate_local populates out_acp with copies created
if (inst->src[i].file != GRF)
continue;
- foreach_list(entry_node, &acp[inst->src[i].reg % ACP_HASH_SIZE]) {
- acp_entry *entry = (acp_entry *)entry_node;
-
+ foreach_in_list(acp_entry, entry, &acp[inst->src[i].reg % ACP_HASH_SIZE]) {
if (try_constant_propagate(brw, inst, entry))
progress = true;
int ip = p->nr_insn;
- foreach_list(node, &this->discard_halt_patches) {
- ip_record *patch_ip = (ip_record *)node;
+ foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
brw_inst *patch = &p->store[patch_ip->ip];
assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
if (unlikely(debug_flag))
cfg = new(mem_ctx) cfg_t(instructions);
- foreach_list(node, instructions) {
- fs_inst *inst = (fs_inst *)node;
+ foreach_in_list(fs_inst, inst, instructions) {
struct brw_reg src[3], dst;
unsigned int last_insn_offset = p->next_insn_offset;
}
this->grf_used = hw_reg_mapping[this->virtual_grf_count];
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *)node;
-
+ foreach_in_list(fs_inst, inst, &instructions) {
assign_reg(hw_reg_mapping, &inst->dst, reg_width);
assign_reg(hw_reg_mapping, &inst->src[0], reg_width);
assign_reg(hw_reg_mapping, &inst->src[1], reg_width);
int payload_last_use_ip[payload_node_count];
memset(payload_last_use_ip, 0, sizeof(payload_last_use_ip));
int ip = 0;
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *)node;
-
+ foreach_in_list(fs_inst, inst, &instructions) {
switch (inst->opcode) {
case BRW_OPCODE_DO:
loop_depth++;
memset(mrf_used, 0, BRW_MAX_MRF * sizeof(bool));
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *)node;
-
+ foreach_in_list(fs_inst, inst, &instructions) {
if (inst->dst.file == MRF) {
int reg = inst->dst.reg & ~BRW_MRF_COMPR4;
mrf_used[reg] = true;
reg_width);
}
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *)node;
-
+ foreach_in_list(fs_inst, inst, &instructions) {
assign_reg(hw_reg_mapping, &inst->dst, reg_width);
assign_reg(hw_reg_mapping, &inst->src[0], reg_width);
assign_reg(hw_reg_mapping, &inst->src[1], reg_width);
* spill/unspill we'll have to do, and guess that the insides of
* loops run 10 times.
*/
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *)node;
-
+ foreach_in_list(fs_inst, inst, &instructions) {
for (unsigned int i = 0; i < inst->sources; i++) {
if (inst->src[i].file == GRF) {
spill_costs[inst->src[i].reg] += loop_scale;
* virtual grf of the same size. For most instructions, though, we
* could just spill/unspill the GRF being accessed.
*/
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *)node;
-
+ foreach_in_list(fs_inst, inst, &instructions) {
for (unsigned int i = 0; i < inst->sources; i++) {
if (inst->src[i].file == GRF &&
inst->src[i].reg == spill_reg) {
int scan_ip = -1;
- foreach_list(n, instructions) {
- fs_inst *scan_inst = (fs_inst *)n;
+ foreach_in_list(fs_inst, scan_inst, instructions) {
scan_ip++;
if (scan_inst->is_control_flow())
int var_to[MAX_SAMPLER_MESSAGE_SIZE];
int var_from[MAX_SAMPLER_MESSAGE_SIZE];
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *)node;
-
+ foreach_in_list(fs_inst, inst, &instructions) {
if (!is_coalesce_candidate(inst, virtual_grf_sizes))
continue;
}
}
- foreach_list(node, &this->instructions) {
- fs_inst *scan_inst = (fs_inst *)node;
-
+ foreach_in_list(fs_inst, scan_inst, &instructions) {
for (int i = 0; i < src_size; i++) {
if (mov[i] || was_load_payload) {
if (scan_inst->dst.file == GRF &&
break;
}
- foreach_list(node, &this->variable_list) {
- variable_entry *entry = (variable_entry *)node;
+ foreach_in_list(variable_entry, entry, &variable_list) {
if (entry->var == var)
return entry;
}
if (!var->type->is_vector())
return NULL;
- foreach_list(node, &*this->variable_list) {
- variable_entry *entry = (variable_entry *)node;
+ foreach_in_list(variable_entry, entry, variable_list) {
if (entry->var == var) {
return entry;
}
/* Replace the decls of the vectors to be split with their split
* components.
*/
- foreach_list(node, &refs.variable_list) {
- variable_entry *entry = (variable_entry *)node;
+ foreach_in_list(variable_entry, entry, &refs.variable_list) {
const struct glsl_type *type;
type = glsl_type::get_instance(entry->var->type->base_type, 1, 1);
}
}
} else if (ir->type->is_record()) {
- foreach_list(node, &ir->components) {
- ir_constant *const field = (ir_constant *) node;
+ foreach_in_list(ir_constant, field, &ir->components) {
const unsigned size = type_size(field->type);
field->accept(this);
emit(IF(BRW_PREDICATE_NORMAL));
}
- foreach_list(node, &ir->then_instructions) {
- ir_instruction *ir = (ir_instruction *)node;
- this->base_ir = ir;
-
- ir->accept(this);
+ foreach_in_list(ir_instruction, ir_, &ir->then_instructions) {
+ this->base_ir = ir_;
+ ir_->accept(this);
}
if (!ir->else_instructions.is_empty()) {
emit(BRW_OPCODE_ELSE);
- foreach_list(node, &ir->else_instructions) {
- ir_instruction *ir = (ir_instruction *)node;
- this->base_ir = ir;
-
- ir->accept(this);
+ foreach_in_list(ir_instruction, ir_, &ir->else_instructions) {
+ this->base_ir = ir_;
+ ir_->accept(this);
}
}
this->base_ir = NULL;
emit(BRW_OPCODE_DO);
- foreach_list(node, &ir->body_instructions) {
- ir_instruction *ir = (ir_instruction *)node;
-
- this->base_ir = ir;
- ir->accept(this);
+ foreach_in_list(ir_instruction, ir_, &ir->body_instructions) {
+ this->base_ir = ir_;
+ ir_->accept(this);
}
this->base_ir = NULL;
assert(sig);
- foreach_list(node, &sig->body) {
- ir_instruction *ir = (ir_instruction *)node;
- this->base_ir = ir;
-
- ir->accept(this);
+ foreach_in_list(ir_instruction, ir_, &sig->body) {
+ this->base_ir = ir_;
+ ir_->accept(this);
}
}
}
memset(last_mrf_write, 0, sizeof(last_mrf_write));
/* top-to-bottom dependencies: RAW and WAW. */
- foreach_list(node, &instructions) {
- schedule_node *n = (schedule_node *)node;
+ foreach_in_list(schedule_node, n, &instructions) {
fs_inst *inst = (fs_inst *)n->inst;
if (inst->opcode == FS_OPCODE_PLACEHOLDER_HALT ||
memset(last_mrf_write, 0, sizeof(last_mrf_write));
/* top-to-bottom dependencies: RAW and WAW. */
- foreach_list(node, &instructions) {
- schedule_node *n = (schedule_node *)node;
+ foreach_in_list(schedule_node, n, &instructions) {
vec4_instruction *inst = (vec4_instruction *)n->inst;
if (inst->has_side_effects())
/* Of the instructions ready to execute or the closest to
* being ready, choose the oldest one.
*/
- foreach_list(node, &instructions) {
- schedule_node *n = (schedule_node *)node;
-
+ foreach_in_list(schedule_node, n, &instructions) {
if (!chosen || n->unblocked_time < chosen_time) {
chosen = n;
chosen_time = n->unblocked_time;
* shaders which naturally do a better job of hiding instruction
* latency.
*/
- foreach_list(node, &instructions) {
- schedule_node *n = (schedule_node *)node;
+ foreach_in_list(schedule_node, n, &instructions) {
fs_inst *inst = (fs_inst *)n->inst;
if (!chosen) {
/* Of the instructions ready to execute or the closest to being ready,
* choose the oldest one.
*/
- foreach_list(node, &instructions) {
- schedule_node *n = (schedule_node *)node;
-
+ foreach_in_list(schedule_node, n, &instructions) {
if (!chosen || n->unblocked_time < chosen_time) {
chosen = n;
chosen_time = n->unblocked_time;
* is done.
*/
if (chosen->inst->is_math()) {
- foreach_list(node, &instructions) {
- schedule_node *n = (schedule_node *)node;
-
+ foreach_in_list(schedule_node, n, &instructions) {
if (n->inst->is_math())
n->unblocked_time = MAX2(n->unblocked_time,
time + chosen->latency);
* scheduling.
*/
if (remaining_grf_uses) {
- foreach_list(node, all_instructions) {
+ foreach_in_list(schedule_node, node, all_instructions) {
count_remaining_grf_uses((backend_instruction *)node);
}
}
}
calculate_deps();
- foreach_list(node, &instructions) {
- schedule_node *n = (schedule_node *)node;
+ foreach_in_list(schedule_node, n, &instructions) {
compute_delay(n);
}
* too late. At that point, the values for the built-in uniforms won't
* get sent to the shader.
*/
- foreach_list(node, shader->base.ir) {
- ir_variable *var = ((ir_instruction *) node)->as_variable();
+ foreach_in_list(ir_instruction, node, shader->base.ir) {
+ ir_variable *var = node->as_variable();
if ((var == NULL) || (var->data.mode != ir_var_uniform)
|| (strncmp(var->name, "gl_", 3) != 0))
}
int ip = 0;
- foreach_list(node, &this->instructions) {
- backend_instruction *inst = (backend_instruction *)node;
+ foreach_in_list(backend_instruction, inst, &instructions) {
if (!name)
fprintf(stderr, "%d: ", ip++);
dump_instruction(inst, file);
* vector. The goal is to make elimination of unused uniform
* components easier later.
*/
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *)node;
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
for (int i = 0 ; i < 3; i++) {
if (inst->src[i].file != UNIFORM)
continue;
* expect unused vector elements when we've moved array access out
* to pull constants, and from some GLSL code generators like wine.
*/
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *)node;
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
for (int i = 0 ; i < 3; i++) {
if (inst->src[i].file != UNIFORM)
continue;
this->uniforms = new_uniform_count;
/* Now, update the instructions for our repacked uniforms. */
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *)node;
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
for (int i = 0 ; i < 3; i++) {
int src = inst->src[i].reg;
{
bool progress = false;
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *)node;
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
switch (inst->opcode) {
case BRW_OPCODE_ADD:
if (inst->src[1].is_zero()) {
/* Check that the instructions are compatible with the registers we're trying
* to split.
*/
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *)node;
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
/* If there's a SEND message loading from a GRF on gen7+, it needs to be
* contiguous.
*/
this->virtual_grf_sizes[i] = 1;
}
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *)node;
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
if (inst->dst.file == GRF && split_grf[inst->dst.reg] &&
inst->dst.reg_offset != 0) {
inst->dst.reg = (new_virtual_grf[inst->dst.reg] +
vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map,
bool interleaved)
{
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *)node;
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
/* We have to support ATTR as a destination for GL_FIXED fixup. */
if (inst->dst.file == ATTR) {
int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset];
memset(&cur_value, 0, sizeof(cur_value));
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *)node;
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
/* This pass only works on basic blocks. If there's flow
* control, throw out all our information and start from
* scratch.
if (unlikely(debug_flag))
cfg = new(mem_ctx) cfg_t(instructions);
- foreach_list(node, instructions) {
- vec4_instruction *inst = (vec4_instruction *)node;
+ foreach_in_list(vec4_instruction, inst, instructions) {
struct brw_reg src[3], dst;
if (unlikely(debug_flag))
* flow.
*/
int ip = 0;
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *)node;
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
for (unsigned int i = 0; i < 3; i++) {
if (inst->src[i].file == GRF) {
int reg = inst->src[i].reg;
virtual_grf_used[i] = false;
}
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *) node;
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
if (inst->dst.file == GRF)
virtual_grf_used[inst->dst.reg] = true;
}
prog_data->total_grf = next;
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *) node;
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
assign(hw_reg_mapping, &inst->dst);
assign(hw_reg_mapping, &inst->src[0]);
assign(hw_reg_mapping, &inst->src[1]);
hw_reg_mapping[i] + virtual_grf_sizes[i]);
}
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *)node;
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
assign(hw_reg_mapping, &inst->dst);
assign(hw_reg_mapping, &inst->src[0]);
assign(hw_reg_mapping, &inst->src[1]);
* spill/unspill we'll have to do, and guess that the insides of
* loops run 10 times.
*/
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *) node;
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
for (unsigned int i = 0; i < 3; i++) {
if (inst->src[i].file == GRF) {
spill_costs[inst->src[i].reg] += loop_scale;
unsigned int spill_offset = c->last_scratch++;
/* Generate spill/unspill instructions for the objects being spilled. */
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *) node;
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
for (unsigned int i = 0; i < 3; i++) {
if (inst->src[i].file == GRF && inst->src[i].reg == spill_reg_nr) {
src_reg spill_reg = inst->src[i];
void
vec4_visitor::visit_instructions(const exec_list *list)
{
- foreach_list(node, list) {
- ir_instruction *ir = (ir_instruction *)node;
-
+ foreach_in_list(ir_instruction, ir, list) {
base_ir = ir;
ir->accept(this);
}
vec4_visitor::emit_constant_values(dst_reg *dst, ir_constant *ir)
{
if (ir->type->base_type == GLSL_TYPE_STRUCT) {
- foreach_list(node, &ir->components) {
- ir_constant *field_value = (ir_constant *)node;
-
+ foreach_in_list(ir_constant, field_value, &ir->components) {
emit_constant_values(dst, field_value);
}
return;
* to scratch due to having any array access on them, and where in
* scratch.
*/
- foreach_list(node, &this->instructions) {
- vec4_instruction *inst = (vec4_instruction *)node;
-
+ foreach_in_list(vec4_instruction, inst, &instructions) {
if (inst->dst.file == GRF && inst->dst.reladdr &&
scratch_loc[inst->dst.reg] == -1) {
scratch_loc[inst->dst.reg] = c->last_scratch;
int ip = nr_inst;
- foreach_list(node, &discard_halt_patches) {
- ip_record *patch_ip = (ip_record *) node;
+ foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
gen8_instruction *patch = &store[patch_ip->ip];
assert(gen8_opcode(patch) == BRW_OPCODE_HALT);
if (unlikely(INTEL_DEBUG & DEBUG_WM))
cfg = new(mem_ctx) cfg_t(instructions);
- foreach_list(node, instructions) {
- fs_inst *ir = (fs_inst *) node;
+ foreach_in_list(fs_inst, ir, instructions) {
struct brw_reg src[3], dst;
if (unlikely(INTEL_DEBUG & DEBUG_WM))
if (unlikely(debug_flag))
cfg = new(mem_ctx) cfg_t(instructions);
- foreach_list(node, instructions) {
- vec4_instruction *ir = (vec4_instruction *) node;
+ foreach_in_list(vec4_instruction, ir, instructions) {
struct brw_reg src[3], dst;
if (unlikely(debug_flag))
projects / mesa.git / commitdiff