gen/fhdl/verilog: set direction to io signals

diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index ec858b26491285d930076ae9e3b3da70a2424a13..70a980fa13c510ee15d8655afc78abf41bf5d73b 100644 (file)
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -207,13 +207,16 @@ def _printheader(f, ios, name, ns, attr_translate,
         if attr:
             r += "\t" + attr
         if sig in inouts:
+            sig.direction = "inout"
             r += "\tinout " + _printsig(ns, sig)
         elif sig in targets:
+            sig.direction = "output"
             if sig in wires:
                 r += "\toutput " + _printsig(ns, sig)
             else:
                 r += "\toutput reg " + _printsig(ns, sig)
         else:
+            sig.direction = "input"
             r += "\tinput " + _printsig(ns, sig)
     r += "\n);\n\n"
     for sig in sorted(sigs - ios, key=lambda x: x.duid):