[system]
type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
+children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
+boot_loader=/work/gem5/dist/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
flags_addr=469827632
gic_cpu_addr=738205696
-have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_3/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
+image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
eventq_index=0
[system.cpu2]
+type=MinorCPU
+children=branchPred dstage2_mmu dtb executeFuncUnits isa istage2_mmu itb tracer
+branchPred=system.cpu2.branchPred
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+decodeCycleInput=true
+decodeInputBufferSize=3
+decodeInputWidth=2
+decodeToExecuteForwardDelay=1
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu2.dstage2_mmu
+dtb=system.cpu2.dtb
+enableIdling=true
+eventq_index=0
+executeAllowEarlyMemoryIssue=true
+executeBranchDelay=1
+executeCommitLimit=2
+executeCycleInput=true
+executeFuncUnits=system.cpu2.executeFuncUnits
+executeInputBufferSize=7
+executeInputWidth=2
+executeIssueLimit=2
+executeLSQMaxStoreBufferStoresPerCycle=2
+executeLSQRequestsQueueSize=1
+executeLSQStoreBufferSize=5
+executeLSQTransfersQueueSize=2
+executeMaxAccessesInMemory=2
+executeMemoryCommitLimit=1
+executeMemoryIssueLimit=1
+executeMemoryWidth=0
+executeSetTraceTimeOnCommit=true
+executeSetTraceTimeOnIssue=false
+fetch1FetchLimit=1
+fetch1LineSnapWidth=0
+fetch1LineWidth=0
+fetch1ToFetch2BackwardDelay=1
+fetch1ToFetch2ForwardDelay=1
+fetch2CycleInput=true
+fetch2InputBufferSize=2
+fetch2ToDecodeForwardDelay=1
+function_trace=false
+function_trace_start=0
+interrupts=Null
+isa=system.cpu2.isa
+istage2_mmu=system.cpu2.istage2_mmu
+itb=system.cpu2.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=true
+system=system
+tracer=system.cpu2.tracer
+workload=
+
+[system.cpu2.branchPred]
+type=TournamentBP
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+eventq_index=0
+globalCtrBits=2
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+
+[system.cpu2.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu2.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu2.dtb
+
+[system.cpu2.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu2.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu2.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu2.dtb]
+type=ArmTLB
+children=walker
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+is_stage2=false
+size=64
+walker=system.cpu2.dtb.walker
+
+[system.cpu2.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu2.executeFuncUnits]
+type=MinorFUPool
+children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
+eventq_index=0
+funcUnits=system.cpu2.executeFuncUnits.funcUnits0 system.cpu2.executeFuncUnits.funcUnits1 system.cpu2.executeFuncUnits.funcUnits2 system.cpu2.executeFuncUnits.funcUnits3 system.cpu2.executeFuncUnits.funcUnits4 system.cpu2.executeFuncUnits.funcUnits5 system.cpu2.executeFuncUnits.funcUnits6
+
+[system.cpu2.executeFuncUnits.funcUnits0]
+type=MinorFU
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+cantForwardFromFUIndices=
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+opLat=3
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+
+[system.cpu2.executeFuncUnits.funcUnits0.opClasses]
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+
+[system.cpu2.executeFuncUnits.funcUnits0.opClasses.opClasses]
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+
+[system.cpu2.executeFuncUnits.funcUnits0.timings]
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+
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+
+[system.cpu2.executeFuncUnits.funcUnits1]
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+
+[system.cpu2.executeFuncUnits.funcUnits1.opClasses]
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+
+[system.cpu2.executeFuncUnits.funcUnits1.opClasses.opClasses]
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+
+[system.cpu2.executeFuncUnits.funcUnits2]
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+
+[system.cpu2.executeFuncUnits.funcUnits2.opClasses]
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+
+[system.cpu2.executeFuncUnits.funcUnits2.opClasses.opClasses]
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+[system.cpu2.executeFuncUnits.funcUnits2.timings]
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+[system.cpu2.executeFuncUnits.funcUnits2.timings.opClasses]
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+
+[system.cpu2.executeFuncUnits.funcUnits3]
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+timings=
+
+[system.cpu2.executeFuncUnits.funcUnits3.opClasses]
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+
+[system.cpu2.executeFuncUnits.funcUnits3.opClasses.opClasses]
+type=MinorOpClass
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+
+[system.cpu2.executeFuncUnits.funcUnits4]
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+cantForwardFromFUIndices=
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+opLat=6
+timings=system.cpu2.executeFuncUnits.funcUnits4.timings
+
+[system.cpu2.executeFuncUnits.funcUnits4.opClasses]
+type=MinorOpClassSet
+children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
+eventq_index=0
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+
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+
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+[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses04]
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+
+[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses06]
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+
+[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses07]
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+[system.cpu2.executeFuncUnits.funcUnits6]
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+[system.cpu2.executeFuncUnits.funcUnits6.opClasses.opClasses1]
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+
+[system.cpu2.isa]
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+
+[system.cpu2.istage2_mmu]
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+[system.cpu2.istage2_mmu.stage2_tlb]
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+
+[system.cpu2.istage2_mmu.stage2_tlb.walker]
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+[system.cpu2.itb]
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+[system.cpu2.itb.walker]
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+
+[system.cpu2.tracer]
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+
+[system.cpu3]
type=DerivO3CPU
children=branchPred dstage2_mmu dtb fuPool isa istage2_mmu itb tracer
LFSTSize=1024
SSITSize=1024
activity=0
backComSize=5
-branchPred=system.cpu2.branchPred
+branchPred=system.cpu3.branchPred
cachePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
-dstage2_mmu=system.cpu2.dstage2_mmu
-dtb=system.cpu2.dtb
+dstage2_mmu=system.cpu3.dstage2_mmu
+dtb=system.cpu3.dtb
eventq_index=0
fetchBufferSize=64
fetchQueueSize=32
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
-fuPool=system.cpu2.fuPool
+fuPool=system.cpu3.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=Null
-isa=system.cpu2.isa
+isa=system.cpu3.isa
issueToExecuteDelay=1
issueWidth=8
-istage2_mmu=system.cpu2.istage2_mmu
-itb=system.cpu2.itb
+istage2_mmu=system.cpu3.istage2_mmu
+itb=system.cpu3.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
store_set_clear_period=250000
switched_out=true
system=system
-tracer=system.cpu2.tracer
+tracer=system.cpu3.tracer
trapLatency=13
wbWidth=8
workload=
-[system.cpu2.branchPred]
+[system.cpu3.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
localPredictorSize=2048
numThreads=1
-[system.cpu2.dstage2_mmu]
+[system.cpu3.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
-stage2_tlb=system.cpu2.dstage2_mmu.stage2_tlb
+stage2_tlb=system.cpu3.dstage2_mmu.stage2_tlb
sys=system
-tlb=system.cpu2.dtb
+tlb=system.cpu3.dtb
-[system.cpu2.dstage2_mmu.stage2_tlb]
+[system.cpu3.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
-walker=system.cpu2.dstage2_mmu.stage2_tlb.walker
+walker=system.cpu3.dstage2_mmu.stage2_tlb.walker
-[system.cpu2.dstage2_mmu.stage2_tlb.walker]
+[system.cpu3.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
num_squash_per_cycle=2
sys=system
-[system.cpu2.dtb]
+[system.cpu3.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
-walker=system.cpu2.dtb.walker
+walker=system.cpu3.dtb.walker
-[system.cpu2.dtb.walker]
+[system.cpu3.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
num_squash_per_cycle=2
sys=system
-[system.cpu2.fuPool]
+[system.cpu3.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
+FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8
eventq_index=0
-[system.cpu2.fuPool.FUList0]
+[system.cpu3.fuPool.FUList0]
type=FUDesc
children=opList
count=6
eventq_index=0
-opList=system.cpu2.fuPool.FUList0.opList
+opList=system.cpu3.fuPool.FUList0.opList
-[system.cpu2.fuPool.FUList0.opList]
+[system.cpu3.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
opClass=IntAlu
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList1]
+[system.cpu3.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
eventq_index=0
-opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
+opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1
-[system.cpu2.fuPool.FUList1.opList0]
+[system.cpu3.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
opClass=IntMult
opLat=3
pipelined=true
-[system.cpu2.fuPool.FUList1.opList1]
+[system.cpu3.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
opClass=IntDiv
opLat=20
pipelined=false
-[system.cpu2.fuPool.FUList2]
+[system.cpu3.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
eventq_index=0
-opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
+opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2
-[system.cpu2.fuPool.FUList2.opList0]
+[system.cpu3.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=FloatAdd
opLat=2
pipelined=true
-[system.cpu2.fuPool.FUList2.opList1]
+[system.cpu3.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatCmp
opLat=2
pipelined=true
-[system.cpu2.fuPool.FUList2.opList2]
+[system.cpu3.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
opClass=FloatCvt
opLat=2
pipelined=true
-[system.cpu2.fuPool.FUList3]
+[system.cpu3.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
eventq_index=0
-opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
+opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2
-[system.cpu2.fuPool.FUList3.opList0]
+[system.cpu3.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=FloatMult
opLat=4
pipelined=true
-[system.cpu2.fuPool.FUList3.opList1]
+[system.cpu3.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
-[system.cpu2.fuPool.FUList3.opList2]
+[system.cpu3.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
opLat=24
pipelined=false
-[system.cpu2.fuPool.FUList4]
+[system.cpu3.fuPool.FUList4]
type=FUDesc
children=opList
count=0
eventq_index=0
-opList=system.cpu2.fuPool.FUList4.opList
+opList=system.cpu3.fuPool.FUList4.opList
-[system.cpu2.fuPool.FUList4.opList]
+[system.cpu3.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5]
+[system.cpu3.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
eventq_index=0
-opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
+opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19
-[system.cpu2.fuPool.FUList5.opList00]
+[system.cpu3.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
opClass=SimdAdd
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList01]
+[system.cpu3.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
opClass=SimdAddAcc
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList02]
+[system.cpu3.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
opClass=SimdAlu
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList03]
+[system.cpu3.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
opClass=SimdCmp
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList04]
+[system.cpu3.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
opClass=SimdCvt
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList05]
+[system.cpu3.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
opClass=SimdMisc
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList06]
+[system.cpu3.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
opClass=SimdMult
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList07]
+[system.cpu3.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
opClass=SimdMultAcc
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList08]
+[system.cpu3.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
opClass=SimdShift
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList09]
+[system.cpu3.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
opClass=SimdShiftAcc
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList10]
+[system.cpu3.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
opClass=SimdSqrt
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList11]
+[system.cpu3.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
opClass=SimdFloatAdd
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList12]
+[system.cpu3.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
opClass=SimdFloatAlu
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList13]
+[system.cpu3.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
opClass=SimdFloatCmp
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList14]
+[system.cpu3.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
opClass=SimdFloatCvt
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList15]
+[system.cpu3.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
opClass=SimdFloatDiv
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList16]
+[system.cpu3.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
opClass=SimdFloatMisc
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList17]
+[system.cpu3.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
opClass=SimdFloatMult
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList18]
+[system.cpu3.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList19]
+[system.cpu3.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
opClass=SimdFloatSqrt
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList6]
+[system.cpu3.fuPool.FUList6]
type=FUDesc
children=opList
count=0
eventq_index=0
-opList=system.cpu2.fuPool.FUList6.opList
+opList=system.cpu3.fuPool.FUList6.opList
-[system.cpu2.fuPool.FUList6.opList]
+[system.cpu3.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList7]
+[system.cpu3.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
eventq_index=0
-opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
+opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1
-[system.cpu2.fuPool.FUList7.opList0]
+[system.cpu3.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList7.opList1]
+[system.cpu3.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList8]
+[system.cpu3.fuPool.FUList8]
type=FUDesc
children=opList
count=1
eventq_index=0
-opList=system.cpu2.fuPool.FUList8.opList
+opList=system.cpu3.fuPool.FUList8.opList
-[system.cpu2.fuPool.FUList8.opList]
+[system.cpu3.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
opClass=IprAccess
opLat=3
pipelined=false
-[system.cpu2.isa]
+[system.cpu3.isa]
type=ArmISA
eventq_index=0
fpsid=1090793632
pmu=Null
system=system
-[system.cpu2.istage2_mmu]
+[system.cpu3.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
-stage2_tlb=system.cpu2.istage2_mmu.stage2_tlb
+stage2_tlb=system.cpu3.istage2_mmu.stage2_tlb
sys=system
-tlb=system.cpu2.itb
+tlb=system.cpu3.itb
-[system.cpu2.istage2_mmu.stage2_tlb]
+[system.cpu3.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
-walker=system.cpu2.istage2_mmu.stage2_tlb.walker
+walker=system.cpu3.istage2_mmu.stage2_tlb.walker
-[system.cpu2.istage2_mmu.stage2_tlb.walker]
+[system.cpu3.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
num_squash_per_cycle=2
sys=system
-[system.cpu2.itb]
+[system.cpu3.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
-walker=system.cpu2.itb.walker
+walker=system.cpu3.itb.walker
-[system.cpu2.itb.walker]
+[system.cpu3.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
num_squash_per_cycle=2
sys=system
-[system.cpu2.tracer]
+[system.cpu3.tracer]
type=ExeTracer
eventq_index=0
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: instruction 'mcr dccimvac' unimplemented
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7330, Bank: 4
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9347, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9490, Bank: 2
warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is not active!
+Command: 1, Timestamp: 3080, Bank: 4
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 2
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: Returning zero for read from miscreg pmcr
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[2]
+warn: CP14 unimplemented crn[0], opc1[4], crm[0], opc2[2]
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: CP14 unimplemented crn[10], opc1[0], crm[4], opc2[3]
warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: CP14 unimplemented crn[2], opc1[2], crm[0], opc2[2]
+warn: instruction 'mcr bpiall' unimplemented
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: instruction 'mcr bpiall' unimplemented
-warn: instruction 'mcr dcisw' unimplemented
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6533, Bank: 1
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Apr 22 2015 10:58:25
-gem5 started Apr 22 2015 12:26:21
-gem5 executing on phenom
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
+gem5 compiled Jul 29 2015 17:36:13
+gem5 started Jul 29 2015 17:36:59
+gem5 executing on e104799-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5/outgoing/gem5_3/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu0.isa: ISA system set to: 0x305ef00 0x305ef00
- 0: system.cpu1.isa: ISA system set to: 0x305ef00 0x305ef00
- 0: system.cpu2.isa: ISA system set to: 0x305ef00 0x305ef00
---------- Begin Simulation Statistics ----------
-sim_seconds 2.817750 # Number of seconds simulated
-sim_ticks 2817750443000 # Number of ticks simulated
-final_tick 2817750443000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.823452 # Number of seconds simulated
+sim_ticks 2823451688000 # Number of ticks simulated
+final_tick 2823451688000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 301376 # Simulator instruction rate (inst/s)
-host_op_rate 365951 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6727532391 # Simulator tick rate (ticks/s)
-host_mem_usage 628096 # Number of bytes of host memory used
-host_seconds 418.84 # Real time elapsed on the host
-sim_insts 126227981 # Number of instructions simulated
-sim_ops 153274395 # Number of ops (including micro ops) simulated
+host_inst_rate 255579 # Simulator instruction rate (inst/s)
+host_op_rate 310019 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5872606908 # Simulator tick rate (ticks/s)
+host_mem_usage 578280 # Number of bytes of host memory used
+host_seconds 480.78 # Real time elapsed on the host
+sim_insts 122878254 # Number of instructions simulated
+sim_ops 149051775 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 653732 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4510496 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 124544 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1058884 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 5696 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 520896 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 4080320 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 538148 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 3049124 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 121344 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 892800 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 2112 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 373376 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 2020416 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.dtb.walker 4416 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 355840 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data 3621312 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10955912 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 653732 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 124544 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 520896 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1299172 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8264128 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8281652 # Number of bytes written to this memory
+system.physmem.bytes_read::total 10980232 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 538148 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 121344 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 373376 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 355840 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1388708 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8266880 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8284404 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 18668 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 70995 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1946 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 16546 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 89 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 8139 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 63755 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 16862 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 48162 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1896 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 13950 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 33 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 5834 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 31569 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.dtb.walker 69 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 5560 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data 56583 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 180159 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 129127 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 133508 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 180539 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 129170 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 133551 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 232005 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1600744 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 44200 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 375791 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 2021 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 184862 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 1448077 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3888177 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 232005 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 44200 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 184862 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 461067 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2932881 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2939101 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2932881 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 190599 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1079928 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 42977 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 316209 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker 748 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 132241 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 715584 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.dtb.walker 1564 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 126030 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 1282583 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3888939 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 190599 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 42977 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 132241 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 126030 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 491848 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2927934 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6207 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2934141 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2927934 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 232005 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 1606960 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 44200 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 375793 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 2021 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 184862 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 1448077 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 341 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6827277 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 90477 # Number of read requests accepted
-system.physmem.writeReqs 65811 # Number of write requests accepted
-system.physmem.readBursts 90477 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 65811 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 5784832 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 5696 # Total number of bytes read from write queue
-system.physmem.bytesWritten 4210432 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 5790468 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 4211784 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 89 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 23137 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 5834 # Per bank write bursts
-system.physmem.perBankRdBursts::1 5704 # Per bank write bursts
-system.physmem.perBankRdBursts::2 5463 # Per bank write bursts
-system.physmem.perBankRdBursts::3 5405 # Per bank write bursts
-system.physmem.perBankRdBursts::4 5372 # Per bank write bursts
-system.physmem.perBankRdBursts::5 5837 # Per bank write bursts
-system.physmem.perBankRdBursts::6 6284 # Per bank write bursts
-system.physmem.perBankRdBursts::7 6486 # Per bank write bursts
-system.physmem.perBankRdBursts::8 6223 # Per bank write bursts
-system.physmem.perBankRdBursts::9 6339 # Per bank write bursts
-system.physmem.perBankRdBursts::10 5440 # Per bank write bursts
-system.physmem.perBankRdBursts::11 5142 # Per bank write bursts
-system.physmem.perBankRdBursts::12 5381 # Per bank write bursts
-system.physmem.perBankRdBursts::13 5279 # Per bank write bursts
-system.physmem.perBankRdBursts::14 4952 # Per bank write bursts
-system.physmem.perBankRdBursts::15 5247 # Per bank write bursts
-system.physmem.perBankWrBursts::0 4133 # Per bank write bursts
-system.physmem.perBankWrBursts::1 3840 # Per bank write bursts
-system.physmem.perBankWrBursts::2 4117 # Per bank write bursts
-system.physmem.perBankWrBursts::3 4118 # Per bank write bursts
-system.physmem.perBankWrBursts::4 3952 # Per bank write bursts
-system.physmem.perBankWrBursts::5 4415 # Per bank write bursts
-system.physmem.perBankWrBursts::6 4512 # Per bank write bursts
-system.physmem.perBankWrBursts::7 4650 # Per bank write bursts
-system.physmem.perBankWrBursts::8 4383 # Per bank write bursts
-system.physmem.perBankWrBursts::9 4609 # Per bank write bursts
-system.physmem.perBankWrBursts::10 3956 # Per bank write bursts
-system.physmem.perBankWrBursts::11 3578 # Per bank write bursts
-system.physmem.perBankWrBursts::12 4192 # Per bank write bursts
-system.physmem.perBankWrBursts::13 4199 # Per bank write bursts
-system.physmem.perBankWrBursts::14 3505 # Per bank write bursts
-system.physmem.perBankWrBursts::15 3629 # Per bank write bursts
+system.physmem.bw_total::cpu0.inst 190599 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1086134 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 42977 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 316209 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 748 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 132241 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 715584 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.dtb.walker 1564 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 126030 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 1282583 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6823080 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 115495 # Number of read requests accepted
+system.physmem.writeReqs 70322 # Number of write requests accepted
+system.physmem.readBursts 115495 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 70322 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 7384064 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue
+system.physmem.bytesWritten 4499904 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 7391680 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 4500608 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 16728 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 7953 # Per bank write bursts
+system.physmem.perBankRdBursts::1 7174 # Per bank write bursts
+system.physmem.perBankRdBursts::2 7640 # Per bank write bursts
+system.physmem.perBankRdBursts::3 7504 # Per bank write bursts
+system.physmem.perBankRdBursts::4 7829 # Per bank write bursts
+system.physmem.perBankRdBursts::5 7364 # Per bank write bursts
+system.physmem.perBankRdBursts::6 7486 # Per bank write bursts
+system.physmem.perBankRdBursts::7 7817 # Per bank write bursts
+system.physmem.perBankRdBursts::8 7059 # Per bank write bursts
+system.physmem.perBankRdBursts::9 7674 # Per bank write bursts
+system.physmem.perBankRdBursts::10 7129 # Per bank write bursts
+system.physmem.perBankRdBursts::11 6171 # Per bank write bursts
+system.physmem.perBankRdBursts::12 6502 # Per bank write bursts
+system.physmem.perBankRdBursts::13 7092 # Per bank write bursts
+system.physmem.perBankRdBursts::14 6785 # Per bank write bursts
+system.physmem.perBankRdBursts::15 6197 # Per bank write bursts
+system.physmem.perBankWrBursts::0 4825 # Per bank write bursts
+system.physmem.perBankWrBursts::1 4280 # Per bank write bursts
+system.physmem.perBankWrBursts::2 4678 # Per bank write bursts
+system.physmem.perBankWrBursts::3 4464 # Per bank write bursts
+system.physmem.perBankWrBursts::4 4644 # Per bank write bursts
+system.physmem.perBankWrBursts::5 4512 # Per bank write bursts
+system.physmem.perBankWrBursts::6 4517 # Per bank write bursts
+system.physmem.perBankWrBursts::7 4571 # Per bank write bursts
+system.physmem.perBankWrBursts::8 4335 # Per bank write bursts
+system.physmem.perBankWrBursts::9 5017 # Per bank write bursts
+system.physmem.perBankWrBursts::10 4515 # Per bank write bursts
+system.physmem.perBankWrBursts::11 3667 # Per bank write bursts
+system.physmem.perBankWrBursts::12 3925 # Per bank write bursts
+system.physmem.perBankWrBursts::13 4539 # Per bank write bursts
+system.physmem.perBankWrBursts::14 4104 # Per bank write bursts
+system.physmem.perBankWrBursts::15 3718 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
-system.physmem.totGap 2816184296500 # Total gap between requests
+system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
+system.physmem.totGap 2821880880500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 1 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 90476 # Read request sizes (log2)
+system.physmem.readPktSize::6 115495 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 2 # Write request sizes (log2)
+system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 65809 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 59474 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 27494 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2874 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 538 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 70322 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 87424 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 24888 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 2511 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 550 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 58 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 54 # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::samples 32481 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 307.722545 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 177.643491 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 335.464678 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 12661 38.98% 38.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 7717 23.76% 62.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 2982 9.18% 71.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 1687 5.19% 77.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 1406 4.33% 81.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 745 2.29% 83.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 513 1.58% 85.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 495 1.52% 86.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 4275 13.16% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 32481 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 3213 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 28.128852 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 487.877717 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 3211 99.94% 99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::26624-27647 1 0.03% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 3213 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 3213 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.475568 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.644293 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 13.368139 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3 6 0.19% 0.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7 1 0.03% 0.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11 1 0.03% 0.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15 2 0.06% 0.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 2703 84.13% 84.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 65 2.02% 86.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 109 3.39% 89.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 35 1.09% 90.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 33 1.03% 91.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 100 3.11% 95.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 9 0.28% 95.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 3 0.09% 95.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 4 0.12% 95.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 8 0.25% 95.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 2 0.06% 95.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 1 0.03% 95.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 103 3.21% 99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 2 0.06% 99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 3 0.09% 99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 4 0.12% 99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 1 0.03% 99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 2 0.06% 99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 1 0.03% 99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 1 0.03% 99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 7 0.22% 99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 1 0.03% 99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151 2 0.06% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 1 0.03% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167 2 0.06% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 1 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 3213 # Writes before turning the bus around for reads
-system.physmem.totQLat 1180806250 # Total ticks spent queuing
-system.physmem.totMemAccLat 2875581250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 451940000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 13063.75 # Average queueing delay per DRAM burst
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+system.physmem.bytesPerActivate::mean 298.674709 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::stdev 326.421202 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1024-1151 4703 11.82% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 39789 # Bytes accessed per row activation
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+system.physmem.rdPerTurnAround::mean 30.804539 # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::36864-38911 1 0.03% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 3745 # Reads before turning the bus around for writes
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+system.physmem.wrPerTurnAround::12-15 5 0.13% 0.40% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::24-27 76 2.03% 93.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 45 1.20% 94.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 29 0.77% 95.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 68 1.82% 97.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 12 0.32% 97.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 10 0.27% 97.65% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::52-55 4 0.11% 97.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 3 0.08% 97.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 1 0.03% 98.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 57 1.52% 99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 4 0.11% 99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 2 0.05% 99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 5 0.13% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 1 0.03% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 1 0.03% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.03% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 3 0.08% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195 1 0.03% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 3745 # Writes before turning the bus around for reads
+system.physmem.totQLat 1373444750 # Total ticks spent queuing
+system.physmem.totMemAccLat 3536744750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 576880000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11904.08 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31813.75 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2.05 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.49 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2.05 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.49 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 30654.08 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.62 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2.62 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 6.07 # Average write queue length when enqueuing
-system.physmem.readRowHits 74627 # Number of row buffer hits during reads
-system.physmem.writeRowHits 49067 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.56 # Row buffer hit rate for writes
-system.physmem.avgGap 18019197.23 # Average gap between requests
-system.physmem.pageHitRate 79.19 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 128285640 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 69757875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 361803000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 218615760 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 178850889360 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 68913339435 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1610809853250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1859352544320 # Total energy per rank (pJ)
-system.physmem_0.averagePower 667.527151 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2632589257000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 91437060000 # Time in different power states
+system.physmem.avgWrQLen 28.79 # Average write queue length when enqueuing
+system.physmem.readRowHits 95547 # Number of row buffer hits during reads
+system.physmem.writeRowHits 50351 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.81 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 71.60 # Row buffer hit rate for writes
+system.physmem.avgGap 15186343.99 # Average gap between requests
+system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 160211520 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 87256125 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 473982600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 236461680 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 179691539040 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 72230311935 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1621102009500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1873981772400 # Total energy per rank (pJ)
+system.physmem_0.averagePower 667.506366 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2640519481750 # Time in different power states
+system.physmem_0.memoryStateTime::REF 91866840000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 14382937750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 18811132750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 117270720 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 63772500 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 343207800 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 207690480 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 178850889360 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 68192676180 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1609047407250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1856822914290 # Total energy per rank (pJ)
-system.physmem_1.averagePower 667.575499 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2633644277500 # Time in different power states
-system.physmem_1.memoryStateTime::REF 91437060000 # Time in different power states
+system.physmem_1.actEnergy 140593320 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 76547625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 425950200 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 219153600 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 179691539040 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 71075732760 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1618530580500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1870160097045 # Total energy per rank (pJ)
+system.physmem_1.averagePower 667.565551 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2642231800750 # Time in different power states
+system.physmem_1.memoryStateTime::REF 91866840000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 13328364750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 17099623500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 5725 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 5725 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples 5725 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 5725 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 5725 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 166068997868 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 0.475665 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev 0.499407 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 87075845118 52.43% 52.43% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1 78993152750 47.57% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 166068997868 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 3165 67.41% 67.41% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1530 32.59% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 4695 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5725 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks 5044 # Table walker walks requested
+system.cpu0.dtb.walker.walksShort 5044 # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples 5044 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 5044 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 5044 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 56727881876 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 1.269097 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 -15265283124 -26.91% -26.91% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1 71993165000 126.91% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 56727881876 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 2868 68.19% 68.19% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M 1338 31.81% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 4206 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5044 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5725 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4695 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5044 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4206 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4695 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 10420 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4206 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 9250 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 14454415 # DTB read hits
-system.cpu0.dtb.read_misses 4808 # DTB read misses
-system.cpu0.dtb.write_hits 11087884 # DTB write hits
-system.cpu0.dtb.write_misses 917 # DTB write misses
-system.cpu0.dtb.flush_tlb 190 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.read_hits 12055693 # DTB read hits
+system.cpu0.dtb.read_misses 4324 # DTB read misses
+system.cpu0.dtb.write_hits 9053768 # DTB write hits
+system.cpu0.dtb.write_misses 720 # DTB write misses
+system.cpu0.dtb.flush_tlb 172 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 369 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3341 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 2916 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 964 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 817 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 218 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 14459223 # DTB read accesses
-system.cpu0.dtb.write_accesses 11088801 # DTB write accesses
+system.cpu0.dtb.perms_faults 183 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 12060017 # DTB read accesses
+system.cpu0.dtb.write_accesses 9054488 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 25542299 # DTB hits
-system.cpu0.dtb.misses 5725 # DTB misses
-system.cpu0.dtb.accesses 25548024 # DTB accesses
+system.cpu0.dtb.hits 21109461 # DTB hits
+system.cpu0.dtb.misses 5044 # DTB misses
+system.cpu0.dtb.accesses 21114505 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 2784 # Table walker walks requested
-system.cpu0.itb.walker.walksShort 2784 # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walkWaitTime::samples 2784 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 2784 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 2784 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 166068997868 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 0.475665 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev 0.499407 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 87075735118 52.43% 52.43% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 78993262750 47.57% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 166068997868 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 1521 75.19% 75.19% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M 502 24.81% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 2023 # Table walker page sizes translated
+system.cpu0.itb.walker.walks 2455 # Table walker walks requested
+system.cpu0.itb.walker.walksShort 2455 # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walkWaitTime::samples 2455 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 2455 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 2455 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 56727881876 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean 1.269099 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 -15265389124 -26.91% -26.91% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1 71993271000 126.91% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 56727881876 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 1346 75.11% 75.11% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M 446 24.89% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 1792 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2784 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2784 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2455 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2455 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2023 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2023 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 4807 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 67912569 # ITB inst hits
-system.cpu0.itb.inst_misses 2784 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1792 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1792 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 4247 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 56652194 # ITB inst hits
+system.cpu0.itb.inst_misses 2455 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 190 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb 172 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 369 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2012 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1791 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 67915353 # ITB inst accesses
-system.cpu0.itb.hits 67912569 # DTB hits
-system.cpu0.itb.misses 2784 # DTB misses
-system.cpu0.itb.accesses 67915353 # DTB accesses
-system.cpu0.numCycles 82537208 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 56654649 # ITB inst accesses
+system.cpu0.itb.hits 56652194 # DTB hits
+system.cpu0.itb.misses 2455 # DTB misses
+system.cpu0.itb.accesses 56654649 # DTB accesses
+system.cpu0.numCycles 68394939 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 66134007 # Number of instructions committed
-system.cpu0.committedOps 80648826 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 70905199 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 5550 # Number of float alu accesses
-system.cpu0.num_func_calls 7283350 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 8754499 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 70905199 # number of integer instructions
-system.cpu0.num_fp_insts 5550 # number of float instructions
-system.cpu0.num_int_register_reads 131519590 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 49325288 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 4326 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 245878640 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 29383702 # number of times the CC registers were written
-system.cpu0.num_mem_refs 26210186 # number of memory refs
-system.cpu0.num_load_insts 14630349 # Number of load instructions
-system.cpu0.num_store_insts 11579837 # Number of store instructions
-system.cpu0.num_idle_cycles 77938505.493998 # Number of idle cycles
-system.cpu0.num_busy_cycles 4598702.506002 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.055717 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.944283 # Percentage of idle cycles
-system.cpu0.Branches 16436363 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 2195 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 55791644 67.98% 67.99% # Class of executed instruction
-system.cpu0.op_class::IntMult 58049 0.07% 68.06% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 4498 0.01% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.06% # Class of executed instruction
-system.cpu0.op_class::MemRead 14630349 17.83% 85.89% # Class of executed instruction
-system.cpu0.op_class::MemWrite 11579837 14.11% 100.00% # Class of executed instruction
+system.cpu0.committedInsts 55195414 # Number of instructions committed
+system.cpu0.committedOps 66855615 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 58673965 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 4653 # Number of float alu accesses
+system.cpu0.num_func_calls 5764786 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 7314754 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 58673965 # number of integer instructions
+system.cpu0.num_fp_insts 4653 # number of float instructions
+system.cpu0.num_int_register_reads 108155823 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 40952580 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 3548 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 1106 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 203459813 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 24562816 # number of times the CC registers were written
+system.cpu0.num_mem_refs 21693456 # number of memory refs
+system.cpu0.num_load_insts 12204686 # Number of load instructions
+system.cpu0.num_store_insts 9488770 # Number of store instructions
+system.cpu0.num_idle_cycles 64604124.391568 # Number of idle cycles
+system.cpu0.num_busy_cycles 3790814.608432 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.055425 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.944575 # Percentage of idle cycles
+system.cpu0.Branches 13394268 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 2179 0.00% 0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 46192687 67.99% 67.99% # Class of executed instruction
+system.cpu0.op_class::IntMult 50556 0.07% 68.07% # Class of executed instruction
+system.cpu0.op_class::IntDiv 0 0.00% 68.07% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 68.07% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 68.07% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 68.07% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 68.07% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 68.07% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 68.07% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 68.07% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 68.07% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 68.07% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 68.07% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 68.07% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 68.07% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 68.07% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 68.07% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 68.07% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.07% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 68.07% # Class of executed instruction
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-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012242 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017979 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.007763 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014695 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020556 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.009000 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14311.214087 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13888.657297 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14002.235176 # average ReadReq mshr miss latency
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-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 48702.930555 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46644.871400 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13751.031158 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13431.557983 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13531.916388 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15982.421875 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13447.812052 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14245.329400 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 18593.750000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18593.750000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23777.328771 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 28489.156549 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27294.867731 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22015.685983 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26434.565886 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25275.186670 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179694.491670 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 199413.265899 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191404.853967 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176813.289760 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 197336.959718 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189067.679073 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 178431.627196 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 198496.364345 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190375.864734 # average overall mshr uncacheable latency
+system.cpu0.dcache.writebacks::writebacks 691721 # number of writebacks
+system.cpu0.dcache.writebacks::total 691721 # number of writebacks
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+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4933 # number of LoadLockedReq MSHR misses
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+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32780 # number of overall MSHR uncacheable misses
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+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3391435500 # number of ReadReq MSHR miss cycles
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 15891500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 52341000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76843000 # number of LoadLockedReq MSHR miss cycles
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+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3553110000 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1200341982 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2725597982 # number of WriteReq MSHR uncacheable cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2292357500 # number of overall MSHR uncacheable cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6278707982 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014087 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018138 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016057 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009055 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012471 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017368 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017736 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009254 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.233562 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.175261 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.238686 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.121950 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.008888 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.014933 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.031783 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010520 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000179 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000037 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013401 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017798 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.016793 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.009141 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.015827 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019619 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019168 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.010395 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15038.475778 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13385.873329 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14347.964026 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14193.907574 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35905.609960 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47073.005392 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50597.498590 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46904.040263 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12835.468399 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13687.762881 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15503.614533 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14383.788604 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12699.852507 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 14433.696639 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16595.117311 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15577.336307 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 26352.941176 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26352.941176 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23279.335471 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27913.900313 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 31142.117848 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28579.218129 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21580.916837 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26443.840026 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29058.350364 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26729.093921 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172546.316557 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 194811.925245 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202408.387353 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192956.989247 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169928.615863 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 190084.563107 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 200023.659723 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189725.600863 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171397.857533 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 192764.673730 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 201353.022271 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191540.817023 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 1799604 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.542681 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 100855692 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1800115 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 56.027360 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 10987259500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 478.414957 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 20.920922 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst 12.206802 # Average occupied blocks per requestor
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+system.cpu0.icache.ReadReq_mshr_misses::total 1234026 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst 210607 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst 478701 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu3.inst 544718 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 1234026 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst 210607 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst 478701 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu3.inst 544718 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 1234026 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2663226000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6160369000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 6946186993 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 15769781993 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2663226000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6160369000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 6946186993 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 15769781993 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2663226000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6160369000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 6946186993 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 15769781993 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045351 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.054490 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012998 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.045351 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.054490 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.012998 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045351 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.054490 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.012998 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12645.477121 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12868.928621 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12751.895463 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12779.132687 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12645.477121 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12868.928621 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12751.895463 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12779.132687 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12645.477121 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12868.928621 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12751.895463 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12779.132687 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 1911 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 1911 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 628 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1283 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 1911 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 1911 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 1911 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 1624 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 12817.118227 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 11165.640992 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 6539.405372 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191 417 25.68% 25.68% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383 849 52.28% 77.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575 357 21.98% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.06% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 1624 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 1004 61.82% 61.82% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 620 38.18% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 1624 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1911 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks 1892 # Table walker walks requested
+system.cpu1.dtb.walker.walksShort 1892 # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 543 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1348 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 1891 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 1891 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 1891 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 1530 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 11241.830065 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 9576.039480 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 6337.675963 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 0.98% 0.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::4096-6143 582 38.04% 39.02% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::10240-12287 519 33.92% 72.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::12288-14335 132 8.63% 81.57% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::14336-16383 18 1.18% 82.75% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::22528-24575 264 17.25% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 1530 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 1775778416 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.436843 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.495995 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 1000042500 56.32% 56.32% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1 775735916 43.68% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 1775778416 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 996 65.14% 65.14% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M 533 34.86% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 1529 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1892 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1911 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1624 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1892 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1529 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1624 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 3535 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1529 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 3421 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 4670594 # DTB read hits
-system.cpu1.dtb.read_misses 1655 # DTB read misses
-system.cpu1.dtb.write_hits 3300164 # DTB write hits
-system.cpu1.dtb.write_misses 256 # DTB write misses
-system.cpu1.dtb.flush_tlb 167 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 123 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.read_hits 3793903 # DTB read hits
+system.cpu1.dtb.read_misses 1653 # DTB read misses
+system.cpu1.dtb.write_hits 2764720 # DTB write hits
+system.cpu1.dtb.write_misses 239 # DTB write misses
+system.cpu1.dtb.flush_tlb 152 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1332 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 1225 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 239 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 65 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 4672249 # DTB read accesses
-system.cpu1.dtb.write_accesses 3300420 # DTB write accesses
+system.cpu1.dtb.perms_faults 70 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 3795556 # DTB read accesses
+system.cpu1.dtb.write_accesses 2764959 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 7970758 # DTB hits
-system.cpu1.dtb.misses 1911 # DTB misses
-system.cpu1.dtb.accesses 7972669 # DTB accesses
+system.cpu1.dtb.hits 6558623 # DTB hits
+system.cpu1.dtb.misses 1892 # DTB misses
+system.cpu1.dtb.accesses 6560515 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 935 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 935 # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1 229 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2 706 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 935 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 935 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 935 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 723 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 13501.383126 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11823.554991 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 6487.735992 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-6143 166 22.96% 22.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::10240-12287 228 31.54% 54.50% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-14335 139 19.23% 73.72% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::14336-16383 7 0.97% 74.69% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::22528-24575 183 25.31% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 723 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 494 68.33% 68.33% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 229 31.67% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 723 # Table walker page sizes translated
+system.cpu1.itb.walker.walks 978 # Table walker walks requested
+system.cpu1.itb.walker.walksShort 978 # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1 197 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2 781 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 978 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 978 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 978 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 708 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 11807.909605 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 9972.994087 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 6711.668965 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-6143 268 37.85% 37.85% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::10240-12287 195 27.54% 65.40% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-14335 96 13.56% 78.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::14336-16383 3 0.42% 79.38% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::22528-24575 146 20.62% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 708 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 1000001500 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 1000001500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 1000001500 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 511 72.18% 72.18% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M 197 27.82% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 708 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 935 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 935 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 978 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 978 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 723 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 723 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 1658 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 22057113 # ITB inst hits
-system.cpu1.itb.inst_misses 935 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 708 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 708 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 1686 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 17734334 # ITB inst hits
+system.cpu1.itb.inst_misses 978 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 167 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 123 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb 152 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 783 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 735 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 22058048 # ITB inst accesses
-system.cpu1.itb.hits 22057113 # DTB hits
-system.cpu1.itb.misses 935 # DTB misses
-system.cpu1.itb.accesses 22058048 # DTB accesses
-system.cpu1.numCycles 158011873 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 17735312 # ITB inst accesses
+system.cpu1.itb.hits 17734334 # DTB hits
+system.cpu1.itb.misses 978 # DTB misses
+system.cpu1.itb.accesses 17735312 # DTB accesses
+system.cpu1.numCycles 143538852 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 21342205 # Number of instructions committed
-system.cpu1.committedOps 25582989 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 22730381 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 1657 # Number of float alu accesses
-system.cpu1.num_func_calls 2417962 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 2740367 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 22730381 # number of integer instructions
-system.cpu1.num_fp_insts 1657 # number of float instructions
-system.cpu1.num_int_register_reads 41903720 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 15946634 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 1337 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 320 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 92962985 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 9452948 # number of times the CC registers were written
-system.cpu1.num_mem_refs 8180627 # number of memory refs
-system.cpu1.num_load_insts 4716601 # Number of load instructions
-system.cpu1.num_store_insts 3464026 # Number of store instructions
-system.cpu1.num_idle_cycles 151538894.643419 # Number of idle cycles
-system.cpu1.num_busy_cycles 6472978.356581 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.040965 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.959035 # Percentage of idle cycles
-system.cpu1.Branches 5307887 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 38 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 18096671 68.81% 68.81% # Class of executed instruction
-system.cpu1.op_class::IntMult 19327 0.07% 68.89% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 1187 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.89% # Class of executed instruction
-system.cpu1.op_class::MemRead 4716601 17.94% 86.83% # Class of executed instruction
-system.cpu1.op_class::MemWrite 3464026 13.17% 100.00% # Class of executed instruction
+system.cpu1.committedInsts 17131755 # Number of instructions committed
+system.cpu1.committedOps 20672467 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 18427801 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 1229 # Number of float alu accesses
+system.cpu1.num_func_calls 2005849 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 2182476 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 18427801 # number of integer instructions
+system.cpu1.num_fp_insts 1229 # number of float instructions
+system.cpu1.num_int_register_reads 34218314 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 12924255 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 840 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 390 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 75293665 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 7369592 # number of times the CC registers were written
+system.cpu1.num_mem_refs 6757135 # number of memory refs
+system.cpu1.num_load_insts 3837451 # Number of load instructions
+system.cpu1.num_store_insts 2919684 # Number of store instructions
+system.cpu1.num_idle_cycles 136561451.428475 # Number of idle cycles
+system.cpu1.num_busy_cycles 6977400.571525 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.048610 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.951390 # Percentage of idle cycles
+system.cpu1.Branches 4295209 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 47 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 14510863 68.17% 68.17% # Class of executed instruction
+system.cpu1.op_class::IntMult 16280 0.08% 68.25% # Class of executed instruction
+system.cpu1.op_class::IntDiv 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 958 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.25% # Class of executed instruction
+system.cpu1.op_class::MemRead 3837451 18.03% 86.28% # Class of executed instruction
+system.cpu1.op_class::MemWrite 2919684 13.72% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 26297850 # Class of executed instruction
+system.cpu1.op_class::total 21285283 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 17205761 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 9385761 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 401350 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 10751395 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 8022189 # Number of BTB hits
+system.cpu2.branchPred.lookups 5610171 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 2857915 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 501995 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 3283896 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 2333083 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 74.615331 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 4025562 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 21207 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 71.046190 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 1583798 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 327364 # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.dtb.walker.walks 43873 # Table walker walks requested
-system.cpu2.dtb.walker.walksShort 43873 # Table walker walks initiated with short descriptors
-system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 13923 # Level at which table walker walks with short descriptors terminate
-system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 10993 # Level at which table walker walks with short descriptors terminate
-system.cpu2.dtb.walker.walksSquashedBefore 18957 # Table walks squashed before starting
-system.cpu2.dtb.walker.walkWaitTime::samples 24916 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::mean 571.078825 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::stdev 3693.718026 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0-16383 24688 99.08% 99.08% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::16384-32767 176 0.71% 99.79% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::32768-49151 30 0.12% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::49152-65535 9 0.04% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::65536-81919 9 0.04% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::98304-114687 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::114688-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::131072-147455 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total 24916 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples 9164 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 13158.828023 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 10878.635204 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev 7680.126787 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-8191 2739 29.89% 29.89% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::8192-16383 3883 42.37% 72.26% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::16384-24575 2316 25.27% 97.53% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::24576-32767 72 0.79% 98.32% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::32768-40959 91 0.99% 99.31% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::40960-49151 60 0.65% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::81920-90111 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total 9164 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walksPending::samples 60380803468 # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::mean 0.564289 # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::stdev 0.516018 # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::0-1 60322207968 99.90% 99.90% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::2-3 41747500 0.07% 99.97% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::4-5 8670500 0.01% 99.99% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::6-7 3297500 0.01% 99.99% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::8-9 1514000 0.00% 99.99% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::10-11 972000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::12-13 454500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::14-15 1161000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::16-17 173500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::18-19 164000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::20-21 123500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::22-23 89000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::24-25 134500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::26-27 15500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::28-29 5500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::30-31 73000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::total 60380803468 # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K 2766 73.10% 73.10% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::1M 1018 26.90% 100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total 3784 # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 43873 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walks 12445 # Table walker walks requested
+system.cpu2.dtb.walker.walksShort 12445 # Table walker walks initiated with short descriptors
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7726 # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4719 # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walkWaitTime::samples 12445 # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0 12445 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total 12445 # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples 2100 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 12636.428571 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 10856.238054 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev 6881.912938 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-8191 609 29.00% 29.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1011 48.14% 77.14% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::16384-24575 478 22.76% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::81920-90111 2 0.10% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total 2100 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walksPending::samples 2000071000 # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::0 2000071000 100.00% 100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::total 2000071000 # Table walker pending requests distribution
+system.cpu2.dtb.walker.walkPageSizes::4K 1328 63.24% 63.24% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::1M 772 36.76% 100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total 2100 # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12445 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 43873 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 3784 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12445 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2100 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 3784 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total 47657 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2100 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total 14545 # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
-system.cpu2.dtb.read_hits 9620013 # DTB read hits
-system.cpu2.dtb.read_misses 37991 # DTB read misses
-system.cpu2.dtb.write_hits 7129568 # DTB write hits
-system.cpu2.dtb.write_misses 5882 # DTB write misses
-system.cpu2.dtb.flush_tlb 179 # Number of times complete TLB was flushed
-system.cpu2.dtb.flush_tlb_mva 348 # Number of times TLB was flushed by MVA
+system.cpu2.dtb.read_hits 4343761 # DTB read hits
+system.cpu2.dtb.read_misses 11112 # DTB read misses
+system.cpu2.dtb.write_hits 3378115 # DTB write hits
+system.cpu2.dtb.write_misses 1333 # DTB write misses
+system.cpu2.dtb.flush_tlb 152 # Number of times complete TLB was flushed
+system.cpu2.dtb.flush_tlb_mva 166 # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries 2312 # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults 478 # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults 974 # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_entries 1535 # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults 222 # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults 301 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults 415 # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses 9658004 # DTB read accesses
-system.cpu2.dtb.write_accesses 7135450 # DTB write accesses
+system.cpu2.dtb.perms_faults 123 # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses 4354873 # DTB read accesses
+system.cpu2.dtb.write_accesses 3379448 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu2.dtb.hits 16749581 # DTB hits
-system.cpu2.dtb.misses 43873 # DTB misses
-system.cpu2.dtb.accesses 16793454 # DTB accesses
+system.cpu2.dtb.hits 7721876 # DTB hits
+system.cpu2.dtb.misses 12445 # DTB misses
+system.cpu2.dtb.accesses 7734321 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.itb.walker.walks 5947 # Table walker walks requested
-system.cpu2.itb.walker.walksShort 5947 # Table walker walks initiated with short descriptors
-system.cpu2.itb.walker.walksShortTerminationLevel::Level1 1786 # Level at which table walker walks with short descriptors terminate
-system.cpu2.itb.walker.walksShortTerminationLevel::Level2 4054 # Level at which table walker walks with short descriptors terminate
-system.cpu2.itb.walker.walksSquashedBefore 107 # Table walks squashed before starting
-system.cpu2.itb.walker.walkWaitTime::samples 5840 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::mean 1732.534247 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::stdev 7455.028366 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0-8191 5455 93.41% 93.41% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::8192-16383 164 2.81% 96.22% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::16384-24575 114 1.95% 98.17% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::24576-32767 45 0.77% 98.94% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::32768-40959 19 0.33% 99.26% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::40960-49151 8 0.14% 99.40% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::49152-57343 13 0.22% 99.62% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::57344-65535 3 0.05% 99.67% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::65536-73727 6 0.10% 99.78% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::73728-81919 3 0.05% 99.83% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::81920-90111 5 0.09% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::90112-98303 1 0.02% 99.93% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::98304-106495 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::106496-114687 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::122880-131071 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total 5840 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples 1844 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 13438.177874 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 11167.697103 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev 8164.078124 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::0-8191 568 30.80% 30.80% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::8192-16383 796 43.17% 73.97% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::16384-24575 418 22.67% 96.64% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::24576-32767 27 1.46% 98.10% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::32768-40959 12 0.65% 98.75% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::40960-49151 15 0.81% 99.57% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::49152-57343 4 0.22% 99.78% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::57344-65535 3 0.16% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::65536-73727 1 0.05% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total 1844 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walksPending::samples 13135820712 # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::mean 0.816052 # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::stdev 0.388899 # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::0 2421306500 18.43% 18.43% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::1 10711149212 81.54% 99.97% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::2 2311000 0.02% 99.99% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::3 636500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::4 285000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::5 97500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::6 35000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::total 13135820712 # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K 1342 77.26% 77.26% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::1M 395 22.74% 100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total 1737 # Table walker page sizes translated
+system.cpu2.itb.walker.walks 1343 # Table walker walks requested
+system.cpu2.itb.walker.walksShort 1343 # Table walker walks initiated with short descriptors
+system.cpu2.itb.walker.walksShortTerminationLevel::Level1 245 # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1098 # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walkWaitTime::samples 1343 # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0 1343 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total 1343 # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples 890 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 12592.696629 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 10799.035256 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev 6603.898577 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::4096-6143 278 31.24% 31.24% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::10240-12287 236 26.52% 57.75% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::12288-14335 167 18.76% 76.52% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::14336-16383 5 0.56% 77.08% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::22528-24575 204 22.92% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total 890 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walksPending::samples 2000056500 # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::0 2000056500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::total 2000056500 # Table walker pending requests distribution
+system.cpu2.itb.walker.walkPageSizes::4K 648 72.81% 72.81% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::1M 242 27.19% 100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total 890 # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 5947 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total 5947 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1343 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1343 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 1737 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total 1737 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total 7684 # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits 12739134 # ITB inst hits
-system.cpu2.itb.inst_misses 5947 # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 890 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total 890 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total 2233 # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits 10557278 # ITB inst hits
+system.cpu2.itb.inst_misses 1343 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
-system.cpu2.itb.flush_tlb 179 # Number of times complete TLB was flushed
-system.cpu2.itb.flush_tlb_mva 348 # Number of times TLB was flushed by MVA
+system.cpu2.itb.flush_tlb 152 # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb_mva 166 # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries 1664 # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries 930 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults 1123 # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults 1750 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.inst_accesses 12745081 # ITB inst accesses
-system.cpu2.itb.hits 12739134 # DTB hits
-system.cpu2.itb.misses 5947 # DTB misses
-system.cpu2.itb.accesses 12745081 # DTB accesses
-system.cpu2.numCycles 69598203 # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses 10558621 # ITB inst accesses
+system.cpu2.itb.hits 10557278 # DTB hits
+system.cpu2.itb.misses 1343 # DTB misses
+system.cpu2.itb.accesses 10558621 # DTB accesses
+system.cpu2.numCycles 1381989702 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 26515709 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 68908003 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 17205761 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 12047751 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 39848524 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 2067901 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 93242 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles 1673 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 258 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 197550 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 103741 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 733 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 12737635 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 269288 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 2836 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 67795354 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.222311 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.353518 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 49366248 72.82% 72.82% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 2347568 3.46% 76.28% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 1568593 2.31% 78.59% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 4737747 6.99% 85.58% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 1131198 1.67% 87.25% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 711180 1.05% 88.30% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 3791892 5.59% 93.89% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 790451 1.17% 95.06% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 3350477 4.94% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 67795354 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.247216 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.990083 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 18554298 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 36869392 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 10385190 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 1060917 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 925294 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 1315001 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 110273 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 59218991 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 355421 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 925294 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 19165450 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 3849841 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 27045066 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 10823220 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 5986178 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 56757014 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 1753 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 886942 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents 164990 # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents 4446768 # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands 58681863 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 260617277 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 63638433 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 4180 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 48518636 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 10163211 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 951510 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 887874 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 5959133 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 10269621 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 7907555 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 1397245 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 1927093 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 54497262 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 673331 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 51805193 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 68913 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 8128009 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 18480591 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 69367 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 67795354 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 0.764141 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.469300 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 47462334 70.01% 70.01% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 6771907 9.99% 80.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 5071293 7.48% 87.48% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 4140398 6.11% 93.58% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 1621050 2.39% 95.98% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 1073842 1.58% 97.56% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 1127363 1.66% 99.22% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 365418 0.54% 99.76% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 161749 0.24% 100.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 67795354 # Number of insts issued each cycle
-system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 78874 9.93% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 1 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.93% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 365128 45.98% 55.91% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 350163 44.09% 100.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 104 0.00% 0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 34340504 66.29% 66.29% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 39551 0.08% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 1 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 1 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 2876 0.01% 66.37% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.37% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.37% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.37% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 9906412 19.12% 85.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 7515741 14.51% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 51805193 # Type of FU issued
-system.cpu2.iq.rate 0.744347 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 794166 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.015330 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 172259378 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 63331070 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 50263649 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 9441 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 4992 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 4167 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 52594172 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 5083 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 269403 # Number of loads that had data forwarded from stores
-system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 1615728 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 1799 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 38192 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 801002 # Number of stores squashed
-system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 130832 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 65205 # Number of times an access to memory failed due to the cache being blocked
-system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 925294 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 3298023 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 403705 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 55280627 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 94381 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 10269621 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 7907555 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 360066 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 33263 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 361678 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 38192 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 184473 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 164818 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 349291 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 51367571 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 9727601 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 393852 # Number of squashed instructions skipped in execute
-system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 110034 # number of nop insts executed
-system.cpu2.iew.exec_refs 17167980 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 9465672 # Number of branches executed
-system.cpu2.iew.exec_stores 7440379 # Number of stores executed
-system.cpu2.iew.exec_rate 0.738059 # Inst execution rate
-system.cpu2.iew.wb_sent 50970582 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 50267816 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 26418019 # num instructions producing a value
-system.cpu2.iew.wb_consumers 45975704 # num instructions consuming a value
-system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 0.722257 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.574608 # average fanout of values written-back
-system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 8162826 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 603964 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 292667 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 66072678 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 0.712969 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.621762 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 48122515 72.83% 72.83% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 8016673 12.13% 84.97% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 3951454 5.98% 90.95% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 1700222 2.57% 93.52% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 874557 1.32% 94.84% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 615125 0.93% 95.77% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 1261958 1.91% 97.68% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 299480 0.45% 98.14% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 1230694 1.86% 100.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 66072678 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 38816949 # Number of instructions committed
-system.cpu2.commit.committedOps 47107760 # Number of ops (including micro ops) committed
-system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 15760446 # Number of memory references committed
-system.cpu2.commit.loads 8653893 # Number of loads committed
-system.cpu2.commit.membars 226862 # Number of memory barriers committed
-system.cpu2.commit.branches 8887739 # Number of branches committed
-system.cpu2.commit.fp_insts 4128 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 41222164 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 1631970 # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 31306209 66.46% 66.46% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 38229 0.08% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 2876 0.01% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 8653893 18.37% 84.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 7106553 15.09% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 47107760 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 1230694 # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads 112781874 # The number of ROB reads
-system.cpu2.rob.rob_writes 112267275 # The number of ROB writes
-system.cpu2.timesIdled 279594 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 1802849 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 5249879064 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 38751769 # Number of Instructions Simulated
-system.cpu2.committedOps 47042580 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 1.796001 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.796001 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.556793 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.556793 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 56233169 # number of integer regfile reads
-system.cpu2.int_regfile_writes 31866388 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 15654 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 13819 # number of floating regfile writes
-system.cpu2.cc_regfile_reads 181781148 # number of cc regfile reads
-system.cpu2.cc_regfile_writes 19208893 # number of cc regfile writes
-system.cpu2.misc_regfile_reads 94223470 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 484431 # number of misc regfile writes
-system.iobus.trans_dist::ReadReq 30182 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30182 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59005 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59005 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54134 # Packet count per connected master and slave (bytes)
+system.cpu2.committedInsts 19375420 # Number of instructions committed
+system.cpu2.committedOps 23493929 # Number of ops (including micro ops) committed
+system.cpu2.discardedOps 1397443 # Number of ops (including micro ops) which were discarded before commit
+system.cpu2.numFetchSuspends 550 # Number of times Execute suspended instruction fetching
+system.cpu2.quiesceCycles 4259392331 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.cpi 71.326955 # CPI: cycles per instruction
+system.cpu2.ipc 0.014020 # IPC: instructions per cycle
+system.cpu2.kern.inst.arm 0 # number of arm instructions executed
+system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.cpu2.tickCycles 41311098 # Number of cycles that the object actually ticked
+system.cpu2.idleCycles 1340678604 # Total number of cycles that the object has spent stopped
+system.cpu3.branchPred.lookups 13646054 # Number of BP lookups
+system.cpu3.branchPred.condPredicted 7543734 # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect 320434 # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups 8619119 # Number of BTB lookups
+system.cpu3.branchPred.BTBHits 6472050 # Number of BTB hits
+system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu3.branchPred.BTBHitPct 75.089461 # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS 3094994 # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect 16257 # Number of incorrect RAS predictions.
+system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu3.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu3.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu3.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu3.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu3.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu3.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu3.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu3.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu3.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu3.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu3.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu3.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu3.dtb.walker.walks 35143 # Table walker walks requested
+system.cpu3.dtb.walker.walksShort 35143 # Table walker walks initiated with short descriptors
+system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 12076 # Level at which table walker walks with short descriptors terminate
+system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7806 # Level at which table walker walks with short descriptors terminate
+system.cpu3.dtb.walker.walksSquashedBefore 15261 # Table walks squashed before starting
+system.cpu3.dtb.walker.walkWaitTime::samples 19882 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::mean 462.453476 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::stdev 3227.731349 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::0-16383 19738 99.28% 99.28% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::16384-32767 120 0.60% 99.88% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::32768-49151 15 0.08% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::49152-65535 2 0.01% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::65536-81919 3 0.02% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::81920-98303 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::98304-114687 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::114688-131071 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::131072-147455 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::total 19882 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkCompletionTime::samples 6311 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::mean 11174.694977 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::gmean 9013.738443 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::stdev 7509.952707 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::0-16383 5234 82.93% 82.93% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::16384-32767 989 15.67% 98.61% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::32768-49151 83 1.32% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::49152-65535 2 0.03% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::total 6311 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walksPending::samples -8699062064 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::mean 0.943227 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::0-1 -8742325064 100.50% 100.50% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::2-3 30532500 -0.35% 100.15% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::4-5 6165000 -0.07% 100.08% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::6-7 1932500 -0.02% 100.05% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::8-9 1510500 -0.02% 100.04% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::10-11 932000 -0.01% 100.03% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::12-13 478000 -0.01% 100.02% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::14-15 1202000 -0.01% 100.01% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::16-17 269000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::18-19 118500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::20-21 46500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::22-23 12000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::24-25 31500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::26-27 8000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::28-29 6000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::30-31 19000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::total -8699062064 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkPageSizes::4K 1800 71.51% 71.51% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::1M 717 28.49% 100.00% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::total 2517 # Table walker page sizes translated
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 35143 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 35143 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2517 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2517 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin::total 37660 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.inst_hits 0 # ITB inst hits
+system.cpu3.dtb.inst_misses 0 # ITB inst misses
+system.cpu3.dtb.read_hits 7578904 # DTB read hits
+system.cpu3.dtb.read_misses 29166 # DTB read misses
+system.cpu3.dtb.write_hits 5839969 # DTB write hits
+system.cpu3.dtb.write_misses 5977 # DTB write misses
+system.cpu3.dtb.flush_tlb 158 # Number of times complete TLB was flushed
+system.cpu3.dtb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA
+system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu3.dtb.flush_entries 1718 # Number of entries that have been flushed from TLB
+system.cpu3.dtb.align_faults 425 # Number of TLB faults due to alignment restrictions
+system.cpu3.dtb.prefetch_faults 723 # Number of TLB faults due to prefetch
+system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu3.dtb.perms_faults 310 # Number of TLB faults due to permissions restrictions
+system.cpu3.dtb.read_accesses 7608070 # DTB read accesses
+system.cpu3.dtb.write_accesses 5845946 # DTB write accesses
+system.cpu3.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu3.dtb.hits 13418873 # DTB hits
+system.cpu3.dtb.misses 35143 # DTB misses
+system.cpu3.dtb.accesses 13454016 # DTB accesses
+system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu3.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu3.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu3.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu3.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu3.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu3.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu3.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu3.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu3.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu3.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu3.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu3.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu3.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu3.itb.walker.walks 4732 # Table walker walks requested
+system.cpu3.itb.walker.walksShort 4732 # Table walker walks initiated with short descriptors
+system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1951 # Level at which table walker walks with short descriptors terminate
+system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2718 # Level at which table walker walks with short descriptors terminate
+system.cpu3.itb.walker.walksSquashedBefore 63 # Table walks squashed before starting
+system.cpu3.itb.walker.walkWaitTime::samples 4669 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::mean 1610.409081 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::stdev 7290.700462 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::0-16383 4501 96.40% 96.40% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::16384-32767 127 2.72% 99.12% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::32768-49151 19 0.41% 99.53% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::49152-65535 9 0.19% 99.72% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::65536-81919 6 0.13% 99.85% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::81920-98303 3 0.06% 99.91% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::98304-114687 2 0.04% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::114688-131071 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::147456-163839 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::total 4669 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkCompletionTime::samples 1251 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::mean 12846.922462 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::gmean 10663.579337 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::stdev 7853.199891 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::0-4095 16 1.28% 1.28% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::4096-8191 403 32.21% 33.49% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::8192-12287 333 26.62% 60.11% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::12288-16383 200 15.99% 76.10% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::16384-20479 15 1.20% 77.30% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::20480-24575 250 19.98% 97.28% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::24576-28671 6 0.48% 97.76% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::28672-32767 4 0.32% 98.08% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::32768-36863 2 0.16% 98.24% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::36864-40959 7 0.56% 98.80% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::40960-45055 12 0.96% 99.76% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::45056-49151 2 0.16% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::57344-61439 1 0.08% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::total 1251 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walksPending::samples -394920472 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::mean -1.156632 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::0 -848106296 214.75% 214.75% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::1 450855824 -114.16% 100.59% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::2 1608500 -0.41% 100.18% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::3 392000 -0.10% 100.08% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::4 207000 -0.05% 100.03% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::5 65000 -0.02% 100.01% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::6 26500 -0.01% 100.01% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::7 31000 -0.01% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::total -394920472 # Table walker pending requests distribution
+system.cpu3.itb.walker.walkPageSizes::4K 859 72.31% 72.31% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::1M 329 27.69% 100.00% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::total 1188 # Table walker page sizes translated
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4732 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4732 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1188 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1188 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin::total 5920 # Table walker requests started/completed, data/inst
+system.cpu3.itb.inst_hits 9997642 # ITB inst hits
+system.cpu3.itb.inst_misses 4732 # ITB inst misses
+system.cpu3.itb.read_hits 0 # DTB read hits
+system.cpu3.itb.read_misses 0 # DTB read misses
+system.cpu3.itb.write_hits 0 # DTB write hits
+system.cpu3.itb.write_misses 0 # DTB write misses
+system.cpu3.itb.flush_tlb 158 # Number of times complete TLB was flushed
+system.cpu3.itb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA
+system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu3.itb.flush_entries 1217 # Number of entries that have been flushed from TLB
+system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu3.itb.perms_faults 676 # Number of TLB faults due to permissions restrictions
+system.cpu3.itb.read_accesses 0 # DTB read accesses
+system.cpu3.itb.write_accesses 0 # DTB write accesses
+system.cpu3.itb.inst_accesses 10002374 # ITB inst accesses
+system.cpu3.itb.hits 9997642 # DTB hits
+system.cpu3.itb.misses 4732 # DTB misses
+system.cpu3.itb.accesses 10002374 # DTB accesses
+system.cpu3.numCycles 55587045 # number of cpu cycles simulated
+system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu3.fetch.icacheStallCycles 20927206 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 54552679 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 13646054 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 9567044 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 32032256 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 1608040 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.TlbCycles 79957 # Number of cycles fetch has spent waiting for tlb
+system.cpu3.fetch.MiscStallCycles 938 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.PendingDrainCycles 213 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu3.fetch.PendingTrapStallCycles 310222 # Number of stall cycles due to pending traps
+system.cpu3.fetch.PendingQuiesceStallCycles 78152 # Number of stall cycles due to pending quiesce instructions
+system.cpu3.fetch.IcacheWaitRetryStallCycles 195 # Number of stall cycles due to full MSHR
+system.cpu3.fetch.CacheLines 9996683 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 215580 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.ItlbSquashes 2118 # Number of outstanding ITLB misses that were squashed
+system.cpu3.fetch.rateDist::samples 54233142 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.214742 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.347105 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 39601274 73.02% 73.02% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 1868483 3.45% 76.47% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 1208105 2.23% 78.69% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 3698353 6.82% 85.51% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 956006 1.76% 87.28% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 647778 1.19% 88.47% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 2970918 5.48% 93.95% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 646722 1.19% 95.14% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 2635503 4.86% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::total 54233142 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.245490 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 0.981392 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 14598894 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 29797113 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 8084772 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 1033348 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 718831 # Number of cycles decode is squashing
+system.cpu3.decode.BranchResolved 1078244 # Number of times decode resolved a branch
+system.cpu3.decode.BranchMispred 86337 # Number of times decode detected a branch misprediction
+system.cpu3.decode.DecodedInsts 47705679 # Number of instructions handled by decode
+system.cpu3.decode.SquashedInsts 276961 # Number of squashed instructions handled by decode
+system.cpu3.rename.SquashCycles 718831 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 15136583 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 3024863 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 21172664 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles 8572569 # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles 5607363 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 45758805 # Number of instructions processed by rename
+system.cpu3.rename.ROBFullEvents 705 # Number of times rename has blocked due to ROB full
+system.cpu3.rename.IQFullEvents 1147656 # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents 110939 # Number of times rename has blocked due to LQ full
+system.cpu3.rename.SQFullEvents 3950348 # Number of times rename has blocked due to SQ full
+system.cpu3.rename.RenamedOperands 47566105 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 210305694 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 51528880 # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups 3583 # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps 39455162 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 8110943 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 731184 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 676901 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 5765226 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 8100915 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 6455257 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 1173886 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 1646906 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 43984199 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 534989 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 41793570 # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued 55806 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined 6489424 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 14897600 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved 57980 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples 54233142 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 0.770628 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.467625 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 37814670 69.73% 69.73% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 5400070 9.96% 79.68% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 4120767 7.60% 87.28% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 3382476 6.24% 93.52% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4 1384183 2.55% 96.07% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 849283 1.57% 97.64% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 885452 1.63% 99.27% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 261249 0.48% 99.75% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8 134992 0.25% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 54233142 # Number of insts issued each cycle
+system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 63553 10.11% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 286976 45.65% 55.76% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 278158 44.24% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu3.iq.FU_type_0::No_OpClass 64 0.00% 0.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 27814370 66.55% 66.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult 30310 0.07% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 2311 0.01% 66.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 66.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 7807777 18.68% 85.31% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 6138736 14.69% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::total 41793570 # Type of FU issued
+system.cpu3.iq.rate 0.751858 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 628687 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.015043 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 138497118 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 51032224 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 40586618 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads 7657 # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes 4185 # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses 3350 # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses 42418091 # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses 4102 # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads 178986 # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu3.iew.lsq.thread0.squashedLoads 1277727 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses 1461 # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 28401 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 648748 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu3.iew.lsq.thread0.rescheduledLoads 106985 # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked 49122 # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu3.iew.iewSquashCycles 718831 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 2574270 # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles 340639 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts 44583748 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 79881 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 8100915 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 6455257 # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts 277620 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents 23691 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents 310856 # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents 28401 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 151779 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 129603 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 281382 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 41441394 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 7665414 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 317113 # Number of squashed instructions skipped in execute
+system.cpu3.iew.exec_swp 0 # number of swp insts executed
+system.cpu3.iew.exec_nop 64560 # number of nop insts executed
+system.cpu3.iew.exec_refs 13741668 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 7578657 # Number of branches executed
+system.cpu3.iew.exec_stores 6076254 # Number of stores executed
+system.cpu3.iew.exec_rate 0.745523 # Inst execution rate
+system.cpu3.iew.wb_sent 41128495 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 40589968 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 21345679 # num instructions producing a value
+system.cpu3.iew.wb_consumers 37833149 # num instructions consuming a value
+system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu3.iew.wb_rate 0.730206 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.564206 # average fanout of values written-back
+system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu3.commit.commitSquashedInsts 6509597 # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls 477009 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts 235228 # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples 52878842 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean 0.719887 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 1.616953 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 38356720 72.54% 72.54% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 6383323 12.07% 84.61% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 3220180 6.09% 90.70% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 1427186 2.70% 93.40% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 783029 1.48% 94.88% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 553691 1.05% 95.93% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 963741 1.82% 97.75% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 249255 0.47% 98.22% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8 941717 1.78% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::total 52878842 # Number of insts commited each cycle
+system.cpu3.commit.committedInsts 31212680 # Number of instructions committed
+system.cpu3.commit.committedOps 38066779 # Number of ops (including micro ops) committed
+system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu3.commit.refs 12629697 # Number of memory references committed
+system.cpu3.commit.loads 6823188 # Number of loads committed
+system.cpu3.commit.membars 185407 # Number of memory barriers committed
+system.cpu3.commit.branches 7131780 # Number of branches committed
+system.cpu3.commit.fp_insts 3315 # Number of committed floating point instructions.
+system.cpu3.commit.int_insts 33217803 # Number of committed integer instructions.
+system.cpu3.commit.function_calls 1242593 # Number of function calls committed.
+system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu 25405548 66.74% 66.74% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult 29226 0.08% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc 2308 0.01% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead 6823188 17.92% 84.75% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite 5806509 15.25% 100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::total 38066779 # Class of committed instruction
+system.cpu3.commit.bw_lim_events 941717 # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads 90938636 # The number of ROB reads
+system.cpu3.rob.rob_writes 90509785 # The number of ROB writes
+system.cpu3.timesIdled 219189 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles 1353903 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles 5161759281 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts 31175665 # Number of Instructions Simulated
+system.cpu3.committedOps 38029764 # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi 1.783027 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 1.783027 # CPI: Total CPI of All Threads
+system.cpu3.ipc 0.560844 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 0.560844 # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads 45482682 # number of integer regfile reads
+system.cpu3.int_regfile_writes 25425363 # number of integer regfile writes
+system.cpu3.fp_regfile_reads 14224 # number of floating regfile reads
+system.cpu3.fp_regfile_writes 12010 # number of floating regfile writes
+system.cpu3.cc_regfile_reads 146149493 # number of cc regfile reads
+system.cpu3.cc_regfile_writes 16057585 # number of cc regfile writes
+system.cpu3.misc_regfile_reads 75089133 # number of misc regfile reads
+system.cpu3.misc_regfile_writes 354942 # number of misc regfile writes
+system.iobus.trans_dist::ReadReq 30152 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30152 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59010 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59010 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54148 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 105422 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67851 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105436 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178324 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67865 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 159079 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480327 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 18337000 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total 159093 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480085 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 23980000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 4000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 1000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 32000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 2698000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 3354000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 85000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 15728000 # Layer occupancy (ticks)
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+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72463.848921 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 72165.345859 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 70109.863896 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 160046.316557 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 182311.628597 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 189908.122768 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 180456.772021 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 158428.615863 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 178584.174757 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 188517.330445 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 178222.817764 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 159336.585699 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 180697.401615 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 189292.625369 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 179477.730323 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 40110 # Transaction distribution
-system.membus.trans_dist::ReadResp 74274 # Transaction distribution
-system.membus.trans_dist::WriteReq 27559 # Transaction distribution
-system.membus.trans_dist::WriteResp 27559 # Transaction distribution
-system.membus.trans_dist::Writeback 129127 # Transaction distribution
-system.membus.trans_dist::CleanEvict 7993 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4555 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4563 # Transaction distribution
-system.membus.trans_dist::ReadExReq 136939 # Transaction distribution
-system.membus.trans_dist::ReadExResp 136939 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 34165 # Transaction distribution
+system.membus.trans_dist::ReadReq 40114 # Transaction distribution
+system.membus.trans_dist::ReadResp 75574 # Transaction distribution
+system.membus.trans_dist::WriteReq 27565 # Transaction distribution
+system.membus.trans_dist::WriteResp 27565 # Transaction distribution
+system.membus.trans_dist::Writeback 129170 # Transaction distribution
+system.membus.trans_dist::CleanEvict 8408 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4530 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4537 # Transaction distribution
+system.membus.trans_dist::ReadExReq 135995 # Transaction distribution
+system.membus.trans_dist::ReadExResp 135995 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 35460 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105422 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2000 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 479379 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 586811 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109150 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 109150 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 695961 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159079 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 480552 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 588004 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109028 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 109028 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 697032 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4000 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16928316 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 17091415 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2324480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2324480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 19415895 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 278 # Total snoops (count)
-system.membus.snoop_fanout::samples 416813 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16952892 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 17116017 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2321600 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2321600 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 19437617 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 336 # Total snoops (count)
+system.membus.snoop_fanout::samples 417611 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 416813 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 417611 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 416813 # Request fanout histogram
-system.membus.reqLayer0.occupancy 45715500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 417611 # Request fanout histogram
+system.membus.reqLayer0.occupancy 56684000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 475000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 698000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 457691597 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 502688198 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 520011564 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 664974257 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 36772084 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 25114094 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 105713 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2441896 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 27559 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 27559 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 756453 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 1923004 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 19 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 2782 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 296176 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 296176 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 1800158 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 536033 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 20704 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5399808 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2615033 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28551 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87799 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 8131191 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115239416 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97644319 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 47800 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 155188 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 213086723 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 121684 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 5505945 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.031256 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.174010 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 112988 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2628707 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 762046 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 2097370 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2799 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2817 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 296581 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 296581 # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq 1978788 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 536947 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 13984 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5930770 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2618508 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27177 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 101121 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 8677576 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 126672504 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97797817 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 44504 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 177192 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 224692017 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 129673 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 5878617 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.031442 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.174509 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 5333849 96.87% 96.87% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 172096 3.13% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 5693781 96.86% 96.86% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 184836 3.14% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 5505945 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 1781656500 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 5878617 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 2191894997 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 172500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 178500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 1404823682 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 679741283 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 1851402273 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 767013811 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 11544481 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 11591991 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 39263676 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 48212755 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu2.kern.inst.arm 0 # number of arm instructions executed
-system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.cpu3.kern.inst.arm 0 # number of arm instructions executed
+system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
[system]
type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
+children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm64
+boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
flags_addr=469827632
gic_cpu_addr=738205696
-have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821
+kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_3/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/home/stever/m5/aarch-system-2014-10/disks/linaro-minimal-aarch64.img
+image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
eventq_index=0
[system.cpu2]
+type=MinorCPU
+children=branchPred dstage2_mmu dtb executeFuncUnits isa istage2_mmu itb tracer
+branchPred=system.cpu2.branchPred
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+decodeCycleInput=true
+decodeInputBufferSize=3
+decodeInputWidth=2
+decodeToExecuteForwardDelay=1
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu2.dstage2_mmu
+dtb=system.cpu2.dtb
+enableIdling=true
+eventq_index=0
+executeAllowEarlyMemoryIssue=true
+executeBranchDelay=1
+executeCommitLimit=2
+executeCycleInput=true
+executeFuncUnits=system.cpu2.executeFuncUnits
+executeInputBufferSize=7
+executeInputWidth=2
+executeIssueLimit=2
+executeLSQMaxStoreBufferStoresPerCycle=2
+executeLSQRequestsQueueSize=1
+executeLSQStoreBufferSize=5
+executeLSQTransfersQueueSize=2
+executeMaxAccessesInMemory=2
+executeMemoryCommitLimit=1
+executeMemoryIssueLimit=1
+executeMemoryWidth=0
+executeSetTraceTimeOnCommit=true
+executeSetTraceTimeOnIssue=false
+fetch1FetchLimit=1
+fetch1LineSnapWidth=0
+fetch1LineWidth=0
+fetch1ToFetch2BackwardDelay=1
+fetch1ToFetch2ForwardDelay=1
+fetch2CycleInput=true
+fetch2InputBufferSize=2
+fetch2ToDecodeForwardDelay=1
+function_trace=false
+function_trace_start=0
+interrupts=Null
+isa=system.cpu2.isa
+istage2_mmu=system.cpu2.istage2_mmu
+itb=system.cpu2.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=true
+system=system
+tracer=system.cpu2.tracer
+workload=
+
+[system.cpu2.branchPred]
+type=TournamentBP
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+eventq_index=0
+globalCtrBits=2
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+
+[system.cpu2.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu2.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu2.dtb
+
+[system.cpu2.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu2.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu2.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu2.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu2.dtb.walker
+
+[system.cpu2.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu2.executeFuncUnits]
+type=MinorFUPool
+children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
+eventq_index=0
+funcUnits=system.cpu2.executeFuncUnits.funcUnits0 system.cpu2.executeFuncUnits.funcUnits1 system.cpu2.executeFuncUnits.funcUnits2 system.cpu2.executeFuncUnits.funcUnits3 system.cpu2.executeFuncUnits.funcUnits4 system.cpu2.executeFuncUnits.funcUnits5 system.cpu2.executeFuncUnits.funcUnits6
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pipelined=true
-[system.cpu2.fuPool.FUList3.opList1]
+[system.cpu3.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
-[system.cpu2.fuPool.FUList3.opList2]
+[system.cpu3.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
opLat=24
pipelined=false
-[system.cpu2.fuPool.FUList4]
+[system.cpu3.fuPool.FUList4]
type=FUDesc
children=opList
count=0
eventq_index=0
-opList=system.cpu2.fuPool.FUList4.opList
+opList=system.cpu3.fuPool.FUList4.opList
-[system.cpu2.fuPool.FUList4.opList]
+[system.cpu3.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5]
+[system.cpu3.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
eventq_index=0
-opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
+opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19
-[system.cpu2.fuPool.FUList5.opList00]
+[system.cpu3.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
opClass=SimdAdd
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList01]
+[system.cpu3.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
opClass=SimdAddAcc
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList02]
+[system.cpu3.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
opClass=SimdAlu
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList03]
+[system.cpu3.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
opClass=SimdCmp
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList04]
+[system.cpu3.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
opClass=SimdCvt
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList05]
+[system.cpu3.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
opClass=SimdMisc
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList06]
+[system.cpu3.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
opClass=SimdMult
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList07]
+[system.cpu3.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
opClass=SimdMultAcc
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList08]
+[system.cpu3.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
opClass=SimdShift
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList09]
+[system.cpu3.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
opClass=SimdShiftAcc
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList10]
+[system.cpu3.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
opClass=SimdSqrt
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList11]
+[system.cpu3.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
opClass=SimdFloatAdd
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList12]
+[system.cpu3.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
opClass=SimdFloatAlu
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList13]
+[system.cpu3.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
opClass=SimdFloatCmp
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList14]
+[system.cpu3.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
opClass=SimdFloatCvt
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList15]
+[system.cpu3.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
opClass=SimdFloatDiv
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList16]
+[system.cpu3.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
opClass=SimdFloatMisc
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList17]
+[system.cpu3.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
opClass=SimdFloatMult
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList18]
+[system.cpu3.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList5.opList19]
+[system.cpu3.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
opClass=SimdFloatSqrt
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList6]
+[system.cpu3.fuPool.FUList6]
type=FUDesc
children=opList
count=0
eventq_index=0
-opList=system.cpu2.fuPool.FUList6.opList
+opList=system.cpu3.fuPool.FUList6.opList
-[system.cpu2.fuPool.FUList6.opList]
+[system.cpu3.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList7]
+[system.cpu3.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
eventq_index=0
-opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
+opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1
-[system.cpu2.fuPool.FUList7.opList0]
+[system.cpu3.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList7.opList1]
+[system.cpu3.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
-[system.cpu2.fuPool.FUList8]
+[system.cpu3.fuPool.FUList8]
type=FUDesc
children=opList
count=1
eventq_index=0
-opList=system.cpu2.fuPool.FUList8.opList
+opList=system.cpu3.fuPool.FUList8.opList
-[system.cpu2.fuPool.FUList8.opList]
+[system.cpu3.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
opClass=IprAccess
opLat=3
pipelined=false
-[system.cpu2.isa]
+[system.cpu3.isa]
type=ArmISA
eventq_index=0
fpsid=1090793632
pmu=Null
system=system
-[system.cpu2.istage2_mmu]
+[system.cpu3.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
-stage2_tlb=system.cpu2.istage2_mmu.stage2_tlb
+stage2_tlb=system.cpu3.istage2_mmu.stage2_tlb
sys=system
-tlb=system.cpu2.itb
+tlb=system.cpu3.itb
-[system.cpu2.istage2_mmu.stage2_tlb]
+[system.cpu3.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
-walker=system.cpu2.istage2_mmu.stage2_tlb.walker
+walker=system.cpu3.istage2_mmu.stage2_tlb.walker
-[system.cpu2.istage2_mmu.stage2_tlb.walker]
+[system.cpu3.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
num_squash_per_cycle=2
sys=system
-[system.cpu2.itb]
+[system.cpu3.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
-walker=system.cpu2.itb.walker
+walker=system.cpu3.itb.walker
-[system.cpu2.itb.walker]
+[system.cpu3.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
num_squash_per_cycle=2
sys=system
-[system.cpu2.tracer]
+[system.cpu3.tracer]
type=ExeTracer
eventq_index=0
warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7336, Bank: 7
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7858, Bank: 6
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11735, Bank: 6
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9145, Bank: 4
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
-Command: 0, Timestamp: 9168, Bank: 3
+Command: 0, Timestamp: 8760, Bank: 1
+WARNING: Bank is not active!
+Command: 1, Timestamp: 5114, Bank: 5
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8083, Bank: 5
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11235, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10118, Bank: 1
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9340, Bank: 4
+WARNING: Bank is already active!
+Command: 0, Timestamp: 12338, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6589, Bank: 3
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7558, Bank: 4
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10171, Bank: 4
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 6
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7635, Bank: 2
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6745, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7145, Bank: 1
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9101, Bank: 7
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9235, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7617, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8572, Bank: 2
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10110, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7448, Bank: 6
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10610, Bank: 5
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8438, Bank: 3
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10259, Bank: 6
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10259, Bank: 1
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10264, Bank: 4
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8662, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8576, Bank: 2
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8938, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7950, Bank: 1
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8022, Bank: 6
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6606, Bank: 1
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7878, Bank: 5
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9487, Bank: 6
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9249, Bank: 5
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9128, Bank: 4
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8447, Bank: 3
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7453, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7135, Bank: 3
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6921, Bank: 2
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7517, Bank: 5
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11967, Bank: 5
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10632, Bank: 3
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11488, Bank: 1
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9421, Bank: 2
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
-Command: 0, Timestamp: 10927, Bank: 6
+Command: 0, Timestamp: 8184, Bank: 5
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 2
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6813, Bank: 1
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6681, Bank: 7
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8640, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10536, Bank: 5
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11511, Bank: 2
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9988, Bank: 2
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8175, Bank: 5
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 5
+Command: 0, Timestamp: 10565, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10659, Bank: 2
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9255, Bank: 4
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11880, Bank: 6
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7102, Bank: 7
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7405, Bank: 1
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9173, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Apr 22 2015 10:58:25
-gem5 started Apr 22 2015 14:18:06
-gem5 executing on phenom
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full
+gem5 compiled Jul 29 2015 17:36:13
+gem5 started Jul 29 2015 18:34:05
+gem5 executing on e104799-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full -re /work/gem5/outgoing/gem5_3/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu0.isa: ISA system set to: 0x47f6c80 0x47f6c80
- 0: system.cpu1.isa: ISA system set to: 0x47f6c80 0x47f6c80
- 0: system.cpu2.isa: ISA system set to: 0x47f6c80 0x47f6c80
---------- Begin Simulation Statistics ----------
-sim_seconds 51.235006 # Number of seconds simulated
-sim_ticks 51235005618500 # Number of ticks simulated
-final_tick 51235005618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 51.276915 # Number of seconds simulated
+sim_ticks 51276914665000 # Number of ticks simulated
+final_tick 51276914665000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 299120 # Simulator instruction rate (inst/s)
-host_op_rate 351506 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 17342892504 # Simulator tick rate (ticks/s)
-host_mem_usage 728488 # Number of bytes of host memory used
-host_seconds 2954.24 # Real time elapsed on the host
-sim_insts 883670074 # Number of instructions simulated
-sim_ops 1038432543 # Number of ops (including micro ops) simulated
+host_inst_rate 268578 # Simulator instruction rate (inst/s)
+host_op_rate 315601 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 16108564651 # Simulator tick rate (ticks/s)
+host_mem_usage 678484 # Number of bytes of host memory used
+host_seconds 3183.21 # Real time elapsed on the host
+sim_insts 854941205 # Number of instructions simulated
+sim_ops 1004625181 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 126592 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 125376 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 2934708 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 51720008 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 38784 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 35712 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 741632 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 9002048 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 95296 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker 86336 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 2270528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 22315456 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 419776 # Number of bytes read from this memory
-system.physmem.bytes_read::total 89912252 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 2934708 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 741632 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 2270528 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5946868 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 77430208 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 83328 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 90048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 2407092 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 43660040 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 20288 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 19392 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 699200 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 6175552 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 32448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker 28928 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 1537920 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 8615616 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.dtb.walker 64768 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.itb.walker 60352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 1793920 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data 16163456 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 420032 # Number of bytes read from this memory
+system.physmem.bytes_read::total 81872380 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 2407092 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 699200 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 1537920 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 1793920 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 6438132 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 69681088 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 77450788 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 1978 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 1959 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 86262 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 808138 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 606 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 558 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 11588 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 140657 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 1489 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker 1349 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 35477 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 348679 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6559 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1445299 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1209847 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 69701668 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 1302 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 1407 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 78018 # Number of read requests responded to by this memory
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system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
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-system.physmem.bw_read::cpu0.itb.walker 2447 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_inst_read::cpu0.inst 57279 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_inst_read::cpu2.inst 44316 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.readReqs 540590 # Number of read requests accepted
-system.physmem.writeReqs 467319 # Number of write requests accepted
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-system.physmem.bytesWritten 29908416 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 34597760 # Total read bytes from the system interface side
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 52057 # Number of requests that are neither read nor write
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-system.physmem.perBankRdBursts::4 35553 # Per bank write bursts
-system.physmem.perBankRdBursts::5 39917 # Per bank write bursts
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-system.physmem.perBankWrBursts::4 31002 # Per bank write bursts
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-system.physmem.perBankWrBursts::14 28130 # Per bank write bursts
-system.physmem.perBankWrBursts::15 27720 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
-system.physmem.totGap 51233860786000 # Total gap between requests
+system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
+system.physmem.totGap 51275914443000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 540590 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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-system.physmem.wrQLenPdf::63 34 # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::mean 249.586227 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 149.482668 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 288.931122 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 115624 44.75% 44.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 63401 24.54% 69.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 24271 9.39% 78.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 12099 4.68% 83.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 9378 3.63% 87.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 5671 2.19% 89.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 4999 1.93% 91.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 3884 1.50% 92.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 19037 7.37% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 258364 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 26815 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 20.147343 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 9.386417 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-15 3084 11.50% 11.50% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::16-31 21562 80.41% 91.91% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::32-47 1686 6.29% 98.20% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::48-63 338 1.26% 99.46% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::64-79 91 0.34% 99.80% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::80-95 28 0.10% 99.90% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::96-111 17 0.06% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::112-127 4 0.01% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::128-143 2 0.01% 99.99% # Reads before turning the bus around for writes
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+system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 35 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 273820 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 240.988445 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 145.225402 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 282.507263 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 125281 45.75% 45.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 68336 24.96% 70.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 24972 9.12% 79.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 12598 4.60% 84.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 9315 3.40% 87.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 5687 2.08% 89.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 4750 1.73% 91.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 3875 1.42% 93.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 19006 6.94% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 273820 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 27019 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 20.349051 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 10.037322 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-15 3255 12.05% 12.05% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::16-31 21302 78.84% 90.89% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::32-47 1883 6.97% 97.86% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::48-63 429 1.59% 99.44% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::64-79 82 0.30% 99.75% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::80-95 50 0.19% 99.93% # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::112-127 5 0.02% 99.97% # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::144-159 2 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::160-175 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::208-223 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::240-255 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::288-303 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 26815 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 26815 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.427522 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.974087 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 6.290252 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3 17 0.06% 0.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7 10 0.04% 0.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11 10 0.04% 0.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15 46 0.17% 0.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 25300 94.35% 94.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 507 1.89% 96.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 249 0.93% 97.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 127 0.47% 97.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 87 0.32% 98.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 125 0.47% 98.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 58 0.22% 98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 14 0.05% 99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 19 0.07% 99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 19 0.07% 99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 12 0.04% 99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 8 0.03% 99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 123 0.46% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 19 0.07% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 20 0.07% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 17 0.06% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 6 0.02% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 3 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 1 0.00% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 2 0.01% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 6 0.02% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151 2 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167 3 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 26815 # Writes before turning the bus around for reads
-system.physmem.totQLat 12836932182 # Total ticks spent queuing
-system.physmem.totMemAccLat 22966638432 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2701255000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 23761.05 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::336-351 1 0.00% 100.00% # Reads before turning the bus around for writes
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+system.physmem.wrPerTurnAround::mean 17.810134 # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::4-7 13 0.05% 0.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11 7 0.03% 0.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15 44 0.16% 0.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 25225 93.36% 93.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 422 1.56% 95.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 332 1.23% 96.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 185 0.68% 97.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 112 0.41% 97.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 204 0.76% 98.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 76 0.28% 98.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 16 0.06% 98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 19 0.07% 98.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 18 0.07% 98.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 23 0.09% 98.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 14 0.05% 98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 191 0.71% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 20 0.07% 99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 23 0.09% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 16 0.06% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 2 0.01% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.00% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 1 0.00% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 2 0.01% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 2 0.01% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.00% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 2 0.01% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 2 0.01% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 14 0.05% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 1 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 2 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167 5 0.02% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 2 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 27019 # Writes before turning the bus around for reads
+system.physmem.totQLat 11443674557 # Total ticks spent queuing
+system.physmem.totMemAccLat 21753380807 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2749255000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 20812.32 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 42511.05 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 0.67 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.58 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 0.68 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.58 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 39562.32 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 0.69 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 0.60 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 0.69 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.60 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.01 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 22.63 # Average write queue length when enqueuing
-system.physmem.readRowHits 422337 # Number of row buffer hits during reads
-system.physmem.writeRowHits 326863 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 78.17 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 69.94 # Row buffer hit rate for writes
-system.physmem.avgGap 50831831.83 # Average gap between requests
-system.physmem.pageHitRate 74.36 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 1022081760 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 555373500 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 2201604600 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 1562664960 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3304577109600 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1165623840135 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 29580668399250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 34056211073805 # Total energy per rank (pJ)
-system.physmem_0.averagePower 667.700210 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 48799941577250 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1689456600000 # Time in different power states
+system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 6.72 # Average write queue length when enqueuing
+system.physmem.readRowHits 421327 # Number of row buffer hits during reads
+system.physmem.writeRowHits 335914 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 76.63 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 69.80 # Row buffer hit rate for writes
+system.physmem.avgGap 49710915.40 # Average gap between requests
+system.physmem.pageHitRate 73.44 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 1064213640 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 579096375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 2201979000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 1596367440 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3310527770160 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1178433187650 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 30013431943500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 34507834557765 # Total energy per rank (pJ)
+system.physmem_0.averagePower 666.879372 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 48871742574250 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1692498860000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 106076762500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 121731845500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 931059360 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 506149875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 2012353200 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 1465445520 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3304577109600 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1160291732670 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 29572164937500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 34041948787725 # Total energy per rank (pJ)
-system.physmem_1.averagePower 667.708167 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 48807751567992 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1689456600000 # Time in different power states
+system.physmem_1.actEnergy 1005865560 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 547383375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 2086788600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 1521886320 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3310527770160 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1173650278320 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 29856307058250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 34345647030585 # Total energy per rank (pJ)
+system.physmem_1.averagePower 667.211846 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 48878835578992 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1692498860000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 98247859258 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 114595771758 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 112814 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 112814 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples 112814 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 112814 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 112814 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 1116892952476 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 0.571172 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev 0.494909 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 478954833976 42.88% 42.88% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1 637938118500 57.12% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 1116892952476 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 81756 84.41% 84.41% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 15104 15.59% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 96860 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 112814 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks 90556 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 90556 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples 90556 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 90556 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 90556 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 391820965788 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 1.505629 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 -198115997962 -50.56% -50.56% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1 589936963750 150.56% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 391820965788 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 66622 84.81% 84.81% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 11928 15.19% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 78550 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90556 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 112814 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96860 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90556 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78550 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96860 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 209674 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78550 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 169106 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 78427319 # DTB read hits
-system.cpu0.dtb.read_misses 84483 # DTB read misses
-system.cpu0.dtb.write_hits 71558713 # DTB write hits
-system.cpu0.dtb.write_misses 28331 # DTB write misses
-system.cpu0.dtb.flush_tlb 1285 # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits 64673225 # DTB read hits
+system.cpu0.dtb.read_misses 68448 # DTB read misses
+system.cpu0.dtb.write_hits 58639149 # DTB write hits
+system.cpu0.dtb.write_misses 22108 # DTB write misses
+system.cpu0.dtb.flush_tlb 1188 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 21339 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 502 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 51365 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid 15858 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 413 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 41832 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 3702 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 2761 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 9826 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 78511802 # DTB read accesses
-system.cpu0.dtb.write_accesses 71587044 # DTB write accesses
+system.cpu0.dtb.perms_faults 7632 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 64741673 # DTB read accesses
+system.cpu0.dtb.write_accesses 58661257 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 149986032 # DTB hits
-system.cpu0.dtb.misses 112814 # DTB misses
-system.cpu0.dtb.accesses 150098846 # DTB accesses
+system.cpu0.dtb.hits 123312374 # DTB hits
+system.cpu0.dtb.misses 90556 # DTB misses
+system.cpu0.dtb.accesses 123402930 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 63116 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 63116 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walkWaitTime::samples 63116 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 63116 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 63116 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 1116892951476 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 0.571207 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev 0.494904 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 478916115976 42.88% 42.88% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 637976835500 57.12% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 1116892951476 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 54727 95.15% 95.15% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 2791 4.85% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 57518 # Table walker page sizes translated
+system.cpu0.itb.walker.walks 54313 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 54313 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples 54313 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 54313 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 54313 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 391820965788 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean 1.505731 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 -198155892462 -50.57% -50.57% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1 589976858250 150.57% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 391820965788 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 47491 95.01% 95.01% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 2494 4.99% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 49985 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 63116 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 63116 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 54313 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 54313 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57518 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57518 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 120634 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 420544157 # ITB inst hits
-system.cpu0.itb.inst_misses 63116 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49985 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49985 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 104298 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 343634485 # ITB inst hits
+system.cpu0.itb.inst_misses 54313 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 1285 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb 1188 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 21339 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 502 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 35909 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 15858 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 413 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 29675 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 420607273 # ITB inst accesses
-system.cpu0.itb.hits 420544157 # DTB hits
-system.cpu0.itb.misses 63116 # DTB misses
-system.cpu0.itb.accesses 420607273 # DTB accesses
-system.cpu0.numCycles 505895917 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 343688798 # ITB inst accesses
+system.cpu0.itb.hits 343634485 # DTB hits
+system.cpu0.itb.misses 54313 # DTB misses
+system.cpu0.itb.accesses 343688798 # DTB accesses
+system.cpu0.numCycles 414612673 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 420346594 # Number of instructions committed
-system.cpu0.committedOps 494579830 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 453915139 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 407993 # Number of float alu accesses
-system.cpu0.num_func_calls 25255441 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 64064604 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 453915139 # number of integer instructions
-system.cpu0.num_fp_insts 407993 # number of float instructions
-system.cpu0.num_int_register_reads 669796814 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 361015506 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 660600 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 338556 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 110996958 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 110750515 # number of times the CC registers were written
-system.cpu0.num_mem_refs 150079107 # number of memory refs
-system.cpu0.num_load_insts 78499668 # Number of load instructions
-system.cpu0.num_store_insts 71579439 # Number of store instructions
-system.cpu0.num_idle_cycles 493874204.516617 # Number of idle cycles
-system.cpu0.num_busy_cycles 12021712.483383 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.023763 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.976237 # Percentage of idle cycles
-system.cpu0.Branches 93830955 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 343614791 69.43% 69.43% # Class of executed instruction
-system.cpu0.op_class::IntMult 1086596 0.22% 69.65% # Class of executed instruction
-system.cpu0.op_class::IntDiv 48369 0.01% 69.66% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.66% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 49130 0.01% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::MemRead 78499668 15.86% 85.54% # Class of executed instruction
-system.cpu0.op_class::MemWrite 71579439 14.46% 100.00% # Class of executed instruction
+system.cpu0.committedInsts 343491459 # Number of instructions committed
+system.cpu0.committedOps 404038438 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 371064332 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 366662 # Number of float alu accesses
+system.cpu0.num_func_calls 20606328 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 52246055 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 371064332 # number of integer instructions
+system.cpu0.num_fp_insts 366662 # number of float instructions
+system.cpu0.num_int_register_reads 542308147 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 294610052 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 579925 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 335816 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 90131130 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 89914881 # number of times the CC registers were written
+system.cpu0.num_mem_refs 123386712 # number of memory refs
+system.cpu0.num_load_insts 64730993 # Number of load instructions
+system.cpu0.num_store_insts 58655719 # Number of store instructions
+system.cpu0.num_idle_cycles 404807579.503922 # Number of idle cycles
+system.cpu0.num_busy_cycles 9805093.496078 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.023649 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.976351 # Percentage of idle cycles
+system.cpu0.Branches 76646162 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 279922003 69.24% 69.24% # Class of executed instruction
+system.cpu0.op_class::IntMult 872785 0.22% 69.46% # Class of executed instruction
+system.cpu0.op_class::IntDiv 43154 0.01% 69.47% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction
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system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1802945000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5394052500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031449 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.030792 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.032114 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019192 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014297 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015019 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.013775 # mshr miss rate for WriteReq accesses
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+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.758151 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.723529 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.730456 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.424347 # mshr miss rate for SoftPFReq accesses
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+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.740707 # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.358510 # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061883 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.056979 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.062530 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036312 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000004 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023286 # mshr miss rate for demand accesses
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+system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.027021 # mshr miss rate for overall accesses
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+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14315.370550 # average ReadReq mshr miss latency
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+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27541.309791 # average WriteReq mshr miss latency
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+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14694.288761 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15627.327374 # average SoftPFReq mshr miss latency
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+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 26754.213125 # average WriteLineReq mshr miss latency
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-system.cpu0.icache.tags.total_refs 610702941 # Total number of references to valid blocks.
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-system.cpu0.icache.tags.warmup_cycle 9090101500 # Cycle when the warmup percentage was hit.
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-system.cpu0.icache.blocked_cycles::no_mshrs 53098 # number of cycles access was blocked
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 40125 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 40125 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6166 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 29054 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 2 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 40123 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 0.299080 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 59.907962 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-1023 40122 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 40123 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 35222 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 25010.164102 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 22134.109650 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 13083.481555 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767 22653 64.31% 64.31% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535 12324 34.99% 99.30% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303 130 0.37% 99.67% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071 82 0.23% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607 11 0.03% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-229375 3 0.01% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::229376-262143 6 0.02% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911 7 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks 31718 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 31718 # Table walker walks initiated with long descriptors
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+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23271 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting
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+system.cpu1.dtb.walker.walkWaitTime::0 31713 100.00% 100.00% # Table walker wait (enqueue to first request) latency
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+system.cpu1.dtb.walker.walkCompletionTime::samples 27838 # Table walker service (enqueue to completion) latency
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+system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
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-system.cpu1.dtb.walker.walksPending::samples -2750429288 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 1.373730 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 1027918000 -37.37% -37.37% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1 -3778347288 137.37% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total -2750429288 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 29054 82.49% 82.49% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 6166 17.51% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 35220 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 40125 # Table walker requests started/completed, data/inst
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+system.cpu1.dtb.walker.walksPending::1 640207284 38.64% 100.00% # Table walker pending requests distribution
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+system.cpu1.dtb.walker.walkPageSizes::4K 23271 83.61% 83.61% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 4562 16.39% 100.00% # Table walker page sizes translated
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-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 40125 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 35220 # Table walker requests started/completed, data/inst
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-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 35220 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 75345 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27833 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 59551 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 25724641 # DTB read hits
-system.cpu1.dtb.read_misses 30962 # DTB read misses
-system.cpu1.dtb.write_hits 23221976 # DTB write hits
-system.cpu1.dtb.write_misses 9163 # DTB write misses
-system.cpu1.dtb.flush_tlb 1277 # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits 20370755 # DTB read hits
+system.cpu1.dtb.read_misses 24112 # DTB read misses
+system.cpu1.dtb.write_hits 18527997 # DTB write hits
+system.cpu1.dtb.write_misses 7606 # DTB write misses
+system.cpu1.dtb.flush_tlb 1180 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 6096 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 163 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 21958 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid 5411 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 128 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 17894 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 1268 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 972 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 2784 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 25755603 # DTB read accesses
-system.cpu1.dtb.write_accesses 23231139 # DTB write accesses
+system.cpu1.dtb.perms_faults 2622 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 20394867 # DTB read accesses
+system.cpu1.dtb.write_accesses 18535603 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 48946617 # DTB hits
-system.cpu1.dtb.misses 40125 # DTB misses
-system.cpu1.dtb.accesses 48986742 # DTB accesses
+system.cpu1.dtb.hits 38898752 # DTB hits
+system.cpu1.dtb.misses 31718 # DTB misses
+system.cpu1.dtb.accesses 38930470 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 23205 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 23205 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1161 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 20405 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 23205 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 23205 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 23205 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 21566 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 27973.105815 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 25131.407006 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 15236.984733 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767 11031 51.15% 51.15% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535 10248 47.52% 98.67% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303 108 0.50% 99.17% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071 142 0.66% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839 2 0.01% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607 12 0.06% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375 2 0.01% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143 10 0.05% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911 2 0.01% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679 6 0.03% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 21566 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 20405 94.62% 94.62% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 1161 5.38% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 21566 # Table walker page sizes translated
+system.cpu1.itb.walker.walks 20303 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 20303 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 913 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 18082 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 20303 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 20303 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 20303 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 18995 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 26989.076073 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 24368.047797 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 13392.289816 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767 10117 53.26% 53.26% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535 8707 45.84% 99.10% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303 60 0.32% 99.42% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071 90 0.47% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839 2 0.01% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607 6 0.03% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375 3 0.02% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143 6 0.03% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679 2 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 18995 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 1000001500 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 1000001500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 1000001500 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 18082 95.19% 95.19% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 913 4.81% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 18995 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 23205 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 23205 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20303 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20303 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 21566 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 21566 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 44771 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 135626159 # ITB inst hits
-system.cpu1.itb.inst_misses 23205 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18995 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18995 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 39298 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 109122746 # ITB inst hits
+system.cpu1.itb.inst_misses 20303 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 1277 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb 1180 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 6096 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 163 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 16107 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 5411 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 128 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 13373 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 135649364 # ITB inst accesses
-system.cpu1.itb.hits 135626159 # DTB hits
-system.cpu1.itb.misses 23205 # DTB misses
-system.cpu1.itb.accesses 135649364 # DTB accesses
-system.cpu1.numCycles 1276121974 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 109143049 # ITB inst accesses
+system.cpu1.itb.hits 109122746 # DTB hits
+system.cpu1.itb.misses 20303 # DTB misses
+system.cpu1.itb.accesses 109143049 # DTB accesses
+system.cpu1.numCycles 1180099858 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 135538016 # Number of instructions committed
-system.cpu1.committedOps 159130731 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 146160247 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 138681 # Number of float alu accesses
-system.cpu1.num_func_calls 7978033 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 20702063 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 146160247 # number of integer instructions
-system.cpu1.num_fp_insts 138681 # number of float instructions
-system.cpu1.num_int_register_reads 211618661 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 115744147 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 219623 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 127108 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 35291781 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 35222922 # number of times the CC registers were written
-system.cpu1.num_mem_refs 48943439 # number of memory refs
-system.cpu1.num_load_insts 25723579 # Number of load instructions
-system.cpu1.num_store_insts 23219860 # Number of store instructions
-system.cpu1.num_idle_cycles 1249309266.868014 # Number of idle cycles
-system.cpu1.num_busy_cycles 26812707.131986 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.021011 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.978989 # Percentage of idle cycles
-system.cpu1.Branches 30260595 # Number of branches fetched
+system.cpu1.committedInsts 109047622 # Number of instructions committed
+system.cpu1.committedOps 127894194 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 117464270 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 113646 # Number of float alu accesses
+system.cpu1.num_func_calls 6418056 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 16543747 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 117464270 # number of integer instructions
+system.cpu1.num_fp_insts 113646 # number of float instructions
+system.cpu1.num_int_register_reads 169880190 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 93121428 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 186254 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 89372 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 28297680 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 28206937 # number of times the CC registers were written
+system.cpu1.num_mem_refs 38895648 # number of memory refs
+system.cpu1.num_load_insts 20369525 # Number of load instructions
+system.cpu1.num_store_insts 18526123 # Number of store instructions
+system.cpu1.num_idle_cycles 1154177022.629432 # Number of idle cycles
+system.cpu1.num_busy_cycles 25922835.370568 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.021967 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.978033 # Percentage of idle cycles
+system.cpu1.Branches 24335155 # Number of branches fetched
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 109906813 69.03% 69.03% # Class of executed instruction
-system.cpu1.op_class::IntMult 333855 0.21% 69.24% # Class of executed instruction
-system.cpu1.op_class::IntDiv 14527 0.01% 69.25% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 20240 0.01% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::MemRead 25723579 16.16% 85.42% # Class of executed instruction
-system.cpu1.op_class::MemWrite 23219860 14.58% 100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 88791781 69.39% 69.39% # Class of executed instruction
+system.cpu1.op_class::IntMult 259621 0.20% 69.59% # Class of executed instruction
+system.cpu1.op_class::IntDiv 10323 0.01% 69.60% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 20 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.60% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 11904 0.01% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::MemRead 20369525 15.92% 85.52% # Class of executed instruction
+system.cpu1.op_class::MemWrite 18526123 14.48% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 159218874 # Class of executed instruction
+system.cpu1.op_class::total 127969318 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 96379868 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 65507682 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 4329047 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 66096416 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 46823178 # Number of BTB hits
+system.cpu2.branchPred.lookups 40525945 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 28226804 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 1998617 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 29685490 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 21101641 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 70.840722 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 12400698 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 133614 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 71.084025 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 4984455 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 337609 # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.dtb.walker.walks 662632 # Table walker walks requested
-system.cpu2.dtb.walker.walksLong 662632 # Table walker walks initiated with long descriptors
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 11252 # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 67139 # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walksSquashedBefore 410741 # Table walks squashed before starting
-system.cpu2.dtb.walker.walkWaitTime::samples 251891 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::mean 2203.738919 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::stdev 12798.903480 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0-65535 250391 99.40% 99.40% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::65536-131071 1085 0.43% 99.84% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::131072-196607 243 0.10% 99.93% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::196608-262143 75 0.03% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::262144-327679 48 0.02% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::327680-393215 26 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::393216-458751 21 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total 251891 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples 304707 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 22494.824536 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 18425.462627 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev 15718.326432 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-65535 298255 97.88% 97.88% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::65536-131071 5951 1.95% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::131072-196607 243 0.08% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::196608-262143 191 0.06% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::262144-327679 38 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::327680-393215 19 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total 304707 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walksPending::samples 640151154620 # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::mean 0.510260 # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::stdev 0.628480 # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::0-3 639427998620 99.89% 99.89% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::4-7 404049000 0.06% 99.95% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::8-11 134377500 0.02% 99.97% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::12-15 87391000 0.01% 99.98% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::16-19 34713500 0.01% 99.99% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::20-23 17695000 0.00% 99.99% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::24-27 17014000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::28-31 22612000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::32-35 4758500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::36-39 448500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::40-43 50500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::44-47 27500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::48-51 19000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::total 640151154620 # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K 67139 85.65% 85.65% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::2M 11252 14.35% 100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total 78391 # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 662632 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walks 94850 # Table walker walks requested
+system.cpu2.dtb.walker.walksLong 94850 # Table walker walks initiated with long descriptors
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 7112 # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 30265 # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walkWaitTime::samples 94850 # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0 94850 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total 94850 # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples 37377 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 24334.778072 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 21415.303868 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev 12070.350338 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-32767 24490 65.52% 65.52% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::32768-65535 12692 33.96% 99.48% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::65536-98303 111 0.30% 99.78% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::98304-131071 62 0.17% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::131072-163839 2 0.01% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::163840-196607 6 0.02% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::196608-229375 3 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::229376-262143 5 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::262144-294911 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total 37377 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walksPending::samples 2000229500 # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::0 2000229500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::total 2000229500 # Table walker pending requests distribution
+system.cpu2.dtb.walker.walkPageSizes::4K 30265 80.97% 80.97% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::2M 7112 19.03% 100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total 37377 # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 94850 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 662632 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 78391 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 94850 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 37377 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 78391 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total 741023 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 37377 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total 132227 # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
-system.cpu2.dtb.read_hits 76683824 # DTB read hits
-system.cpu2.dtb.read_misses 455088 # DTB read misses
-system.cpu2.dtb.write_hits 59509350 # DTB write hits
-system.cpu2.dtb.write_misses 207544 # DTB write misses
-system.cpu2.dtb.flush_tlb 1276 # Number of times complete TLB was flushed
+system.cpu2.dtb.read_hits 28616458 # DTB read hits
+system.cpu2.dtb.read_misses 79197 # DTB read misses
+system.cpu2.dtb.write_hits 25171351 # DTB write hits
+system.cpu2.dtb.write_misses 15653 # DTB write misses
+system.cpu2.dtb.flush_tlb 1181 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid 14760 # Number of times TLB was flushed by MVA & ASID
-system.cpu2.dtb.flush_tlb_asid 390 # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries 38772 # Number of entries that have been flushed from TLB
+system.cpu2.dtb.flush_tlb_mva_asid 6998 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_asid 187 # Number of times TLB was flushed by ASID
+system.cpu2.dtb.flush_entries 22525 # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults 82 # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults 6499 # Number of TLB faults due to prefetch
+system.cpu2.dtb.prefetch_faults 2323 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults 41159 # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses 77138912 # DTB read accesses
-system.cpu2.dtb.write_accesses 59716894 # DTB write accesses
+system.cpu2.dtb.perms_faults 3900 # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses 28695655 # DTB read accesses
+system.cpu2.dtb.write_accesses 25187004 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu2.dtb.hits 136193174 # DTB hits
-system.cpu2.dtb.misses 662632 # DTB misses
-system.cpu2.dtb.accesses 136855806 # DTB accesses
+system.cpu2.dtb.hits 53787809 # DTB hits
+system.cpu2.dtb.misses 94850 # DTB misses
+system.cpu2.dtb.accesses 53882659 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.itb.walker.walks 81585 # Table walker walks requested
-system.cpu2.itb.walker.walksLong 81585 # Table walker walks initiated with long descriptors
-system.cpu2.itb.walker.walksLongTerminationLevel::Level2 2498 # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walksLongTerminationLevel::Level3 56536 # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walksSquashedBefore 10896 # Table walks squashed before starting
-system.cpu2.itb.walker.walkWaitTime::samples 70689 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::mean 1473.991710 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::stdev 8586.891139 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0-32767 70027 99.06% 99.06% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::32768-65535 428 0.61% 99.67% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::65536-98303 144 0.20% 99.87% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::98304-131071 50 0.07% 99.94% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::131072-163839 13 0.02% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::163840-196607 13 0.02% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::294912-327679 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total 70689 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples 69930 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 28234.749035 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 24509.520790 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev 16350.855698 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::0-32767 36490 52.18% 52.18% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::32768-65535 32158 45.99% 98.17% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::65536-98303 628 0.90% 99.06% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::98304-131071 491 0.70% 99.77% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::131072-163839 45 0.06% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::163840-196607 57 0.08% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::196608-229375 23 0.03% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::229376-262143 10 0.01% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::262144-294911 12 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::360448-393215 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total 69930 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walksPending::samples 485530683964 # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::mean 0.892648 # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::stdev 0.309939 # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::0 52174022580 10.75% 10.75% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::1 433310679884 89.24% 99.99% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::2 41019000 0.01% 100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::3 4632000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::4 311000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::5 12000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::6 6000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::7 1500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::total 485530683964 # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K 56536 95.77% 95.77% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::2M 2498 4.23% 100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total 59034 # Table walker page sizes translated
+system.cpu2.itb.walker.walks 27487 # Table walker walks requested
+system.cpu2.itb.walker.walksLong 27487 # Table walker walks initiated with long descriptors
+system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1835 # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22882 # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walkWaitTime::samples 27487 # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0 27487 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total 27487 # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples 24717 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 27209.107092 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 24621.462305 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev 12743.919659 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::0-32767 12896 52.17% 52.17% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::32768-65535 11567 46.80% 98.97% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::65536-98303 97 0.39% 99.36% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::98304-131071 138 0.56% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::131072-163839 3 0.01% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::163840-196607 7 0.03% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::196608-229375 6 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::229376-262143 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::294912-327679 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total 24717 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walksPending::samples 2000203500 # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::0 2000203500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::total 2000203500 # Table walker pending requests distribution
+system.cpu2.itb.walker.walkPageSizes::4K 22882 92.58% 92.58% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::2M 1835 7.42% 100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total 24717 # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 81585 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total 81585 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27487 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27487 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 59034 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total 59034 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total 140619 # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits 69601857 # ITB inst hits
-system.cpu2.itb.inst_misses 81585 # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24717 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24717 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total 52204 # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits 70482542 # ITB inst hits
+system.cpu2.itb.inst_misses 27487 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
-system.cpu2.itb.flush_tlb 1276 # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb 1181 # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid 14760 # Number of times TLB was flushed by MVA & ASID
-system.cpu2.itb.flush_tlb_asid 390 # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries 30530 # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_tlb_mva_asid 6998 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_asid 187 # Number of times TLB was flushed by ASID
+system.cpu2.itb.flush_entries 17121 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults 148496 # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults 57866 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.inst_accesses 69683442 # ITB inst accesses
-system.cpu2.itb.hits 69601857 # DTB hits
-system.cpu2.itb.misses 81585 # DTB misses
-system.cpu2.itb.accesses 69683442 # DTB accesses
-system.cpu2.numCycles 461100419 # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses 70510029 # ITB inst accesses
+system.cpu2.itb.hits 70482542 # DTB hits
+system.cpu2.itb.misses 27487 # DTB misses
+system.cpu2.itb.accesses 70510029 # DTB accesses
+system.cpu2.numCycles 6664328122 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 177123206 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 428437277 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 96379868 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 59223876 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 257401667 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 9762973 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 2005280 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles 7949 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 2437 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 3773015 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 114784 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 5106 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 69429398 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 2656278 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 32686 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 445314772 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.124877 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.366658 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 339836575 76.31% 76.31% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 13185142 2.96% 79.27% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 13574991 3.05% 82.32% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 9797674 2.20% 84.52% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 20004635 4.49% 89.02% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 6578482 1.48% 90.49% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 7061868 1.59% 92.08% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 6288982 1.41% 93.49% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 28986423 6.51% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 445314772 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.209021 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.929163 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 144945569 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 209061419 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 78115064 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 9308814 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 3881927 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 14332703 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 1014310 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 468249315 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 3113109 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 3881927 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 150342023 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 16281945 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 167363518 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 81901775 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 25541188 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 457027313 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 55411 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 1577150 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents 1077305 # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents 12432724 # Number of times rename has blocked due to SQ full
-system.cpu2.rename.FullRegisterEvents 2850 # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands 436738370 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 696876474 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 538877799 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 611175 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 365603185 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 71135185 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 10148334 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 8698822 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 51282276 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 73817911 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 62641049 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 9297155 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 10241835 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 434108561 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 10116895 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 433413553 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 631683 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 59503474 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 37916216 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 236413 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 445314772 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 0.973275 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.689353 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 278168249 62.47% 62.47% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 68048730 15.28% 77.75% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 31692331 7.12% 84.86% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 22597394 5.07% 89.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 16978227 3.81% 93.75% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 11874624 2.67% 96.42% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 7985798 1.79% 98.21% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 4768189 1.07% 99.28% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 3201230 0.72% 100.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 445314772 # Number of insts issued each cycle
-system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 2163580 25.08% 25.08% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 17452 0.20% 25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 1463 0.02% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.30% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 3490107 40.46% 65.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 2952914 34.23% 100.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 293684501 67.76% 67.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 1025227 0.24% 68.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 47766 0.01% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 317 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 1 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 48576 0.01% 68.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 68.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 78271434 18.06% 86.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 60335731 13.92% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 433413553 # Type of FU issued
-system.cpu2.iq.rate 0.939955 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 8625516 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.019901 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 1320585789 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 503812289 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 417285848 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 813288 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 405263 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 361974 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 441604210 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 434859 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 3381259 # Number of loads that had data forwarded from stores
-system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 11998288 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 16552 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 496769 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 6557326 # Number of stores squashed
-system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 2684885 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 5754188 # Number of times an access to memory failed due to the cache being blocked
-system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 3881927 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 10679636 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 4407291 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 444323917 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 1337797 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 73817911 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 62641049 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 8508217 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 157244 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 4192594 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 496769 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 2009659 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 1725096 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 3734755 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 428275662 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 76671253 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 4484086 # Number of squashed instructions skipped in execute
-system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 98461 # number of nop insts executed
-system.cpu2.iew.exec_refs 136179692 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 79539500 # Number of branches executed
-system.cpu2.iew.exec_stores 59508439 # Number of stores executed
-system.cpu2.iew.exec_rate 0.928812 # Inst execution rate
-system.cpu2.iew.wb_sent 418566552 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 417647822 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 206637380 # num instructions producing a value
-system.cpu2.iew.wb_consumers 358874398 # num instructions consuming a value
-system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 0.905763 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.575793 # average fanout of values written-back
-system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 59540982 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 9880482 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 3329329 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 435241532 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 0.883928 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.881300 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 296713491 68.17% 68.17% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 66287598 15.23% 83.40% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 24183303 5.56% 88.96% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 11166549 2.57% 91.52% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 8012002 1.84% 93.36% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 4870056 1.12% 94.48% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 4489994 1.03% 95.52% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 2918433 0.67% 96.19% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 16600106 3.81% 100.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 435241532 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 327785464 # Number of instructions committed
-system.cpu2.commit.committedOps 384721982 # Number of ops (including micro ops) committed
-system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 117903346 # Number of memory references committed
-system.cpu2.commit.loads 61819623 # Number of loads committed
-system.cpu2.commit.membars 2573370 # Number of memory barriers committed
-system.cpu2.commit.branches 73211237 # Number of branches committed
-system.cpu2.commit.fp_insts 346819 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 353394375 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 9534563 # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 265954850 69.13% 69.13% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 786882 0.20% 69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 35653 0.01% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 41251 0.01% 69.35% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 69.35% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.35% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.35% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 61819623 16.07% 85.42% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 56083723 14.58% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 384721982 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 16600106 # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads 860271406 # The number of ROB reads
-system.cpu2.rob.rob_writes 898612976 # The number of ROB writes
-system.cpu2.timesIdled 2954119 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 15785647 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 99456385277 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 327785464 # Number of Instructions Simulated
-system.cpu2.committedOps 384721982 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 1.406714 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.406714 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.710877 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.710877 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 503674657 # number of integer regfile reads
-system.cpu2.int_regfile_writes 298593848 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 690106 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 421944 # number of floating regfile writes
-system.cpu2.cc_regfile_reads 91580916 # number of cc regfile reads
-system.cpu2.cc_regfile_writes 92419773 # number of cc regfile writes
-system.cpu2.misc_regfile_reads 837090025 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 9982057 # number of misc regfile writes
-system.iobus.trans_dist::ReadReq 40263 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40263 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136537 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136537 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47686 # Packet count per connected master and slave (bytes)
+system.cpu2.committedInsts 147830191 # Number of instructions committed
+system.cpu2.committedOps 173473680 # Number of ops (including micro ops) committed
+system.cpu2.discardedOps 14792725 # Number of ops (including micro ops) which were discarded before commit
+system.cpu2.numFetchSuspends 1537 # Number of times Execute suspended instruction fetching
+system.cpu2.quiesceCycles 95888456497 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.cpi 45.080968 # CPI: cycles per instruction
+system.cpu2.ipc 0.022182 # IPC: instructions per cycle
+system.cpu2.kern.inst.arm 0 # number of arm instructions executed
+system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.cpu2.tickCycles 277268742 # Number of cycles that the object actually ticked
+system.cpu2.idleCycles 6387059380 # Total number of cycles that the object has spent stopped
+system.cpu3.branchPred.lookups 75157877 # Number of BP lookups
+system.cpu3.branchPred.condPredicted 50856390 # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect 3416721 # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups 51465907 # Number of BTB lookups
+system.cpu3.branchPred.BTBHits 36468064 # Number of BTB hits
+system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu3.branchPred.BTBHitPct 70.858683 # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS 9896161 # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect 105828 # Number of incorrect RAS predictions.
+system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu3.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu3.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu3.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu3.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu3.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu3.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu3.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu3.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu3.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu3.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu3.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu3.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu3.dtb.walker.walks 516175 # Table walker walks requested
+system.cpu3.dtb.walker.walksLong 516175 # Table walker walks initiated with long descriptors
+system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8289 # Level at which table walker walks with long descriptors terminate
+system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 49802 # Level at which table walker walks with long descriptors terminate
+system.cpu3.dtb.walker.walksSquashedBefore 319657 # Table walks squashed before starting
+system.cpu3.dtb.walker.walkWaitTime::samples 196518 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::mean 2097.090343 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::stdev 12006.037085 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::0-65535 195408 99.44% 99.44% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::65536-131071 810 0.41% 99.85% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::131072-196607 191 0.10% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::196608-262143 57 0.03% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::262144-327679 27 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::327680-393215 12 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::393216-458751 11 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::total 196518 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkCompletionTime::samples 233052 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::mean 21512.128195 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::gmean 17601.941392 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::stdev 14913.346295 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::0-65535 228911 98.22% 98.22% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3858 1.66% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::131072-196607 119 0.05% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::196608-262143 117 0.05% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::262144-327679 29 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::327680-393215 13 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::total 233052 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walksPending::samples -26470108720 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::mean 0.558973 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::0-3 -27011428720 102.05% 102.05% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::4-7 297974000 -1.13% 100.92% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::8-11 102453500 -0.39% 100.53% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::12-15 64308500 -0.24% 100.29% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::16-19 26659500 -0.10% 100.19% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::20-23 13977000 -0.05% 100.14% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::24-27 12432000 -0.05% 100.09% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::28-31 20278500 -0.08% 100.01% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::32-35 3004000 -0.01% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::36-39 171500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::40-43 49500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::44-47 10000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::48-51 2000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::total -26470108720 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkPageSizes::4K 49802 85.73% 85.73% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::2M 8289 14.27% 100.00% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::total 58091 # Table walker page sizes translated
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 516175 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 516175 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 58091 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 58091 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin::total 574266 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.inst_hits 0 # ITB inst hits
+system.cpu3.dtb.inst_misses 0 # ITB inst misses
+system.cpu3.dtb.read_hits 59190068 # DTB read hits
+system.cpu3.dtb.read_misses 354265 # DTB read misses
+system.cpu3.dtb.write_hits 46339519 # DTB write hits
+system.cpu3.dtb.write_misses 161910 # DTB write misses
+system.cpu3.dtb.flush_tlb 1179 # Number of times complete TLB was flushed
+system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu3.dtb.flush_tlb_mva_asid 11674 # Number of times TLB was flushed by MVA & ASID
+system.cpu3.dtb.flush_tlb_asid 299 # Number of times TLB was flushed by ASID
+system.cpu3.dtb.flush_entries 28883 # Number of entries that have been flushed from TLB
+system.cpu3.dtb.align_faults 57 # Number of TLB faults due to alignment restrictions
+system.cpu3.dtb.prefetch_faults 5029 # Number of TLB faults due to prefetch
+system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu3.dtb.perms_faults 29040 # Number of TLB faults due to permissions restrictions
+system.cpu3.dtb.read_accesses 59544333 # DTB read accesses
+system.cpu3.dtb.write_accesses 46501429 # DTB write accesses
+system.cpu3.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu3.dtb.hits 105529587 # DTB hits
+system.cpu3.dtb.misses 516175 # DTB misses
+system.cpu3.dtb.accesses 106045762 # DTB accesses
+system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu3.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu3.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu3.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu3.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu3.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu3.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu3.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu3.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu3.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu3.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu3.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu3.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu3.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu3.itb.walker.walks 59515 # Table walker walks requested
+system.cpu3.itb.walker.walksLong 59515 # Table walker walks initiated with long descriptors
+system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1820 # Level at which table walker walks with long descriptors terminate
+system.cpu3.itb.walker.walksLongTerminationLevel::Level3 40428 # Level at which table walker walks with long descriptors terminate
+system.cpu3.itb.walker.walksSquashedBefore 8158 # Table walks squashed before starting
+system.cpu3.itb.walker.walkWaitTime::samples 51357 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::mean 1446.696653 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::stdev 8669.763957 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::0-32767 50895 99.10% 99.10% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::32768-65535 295 0.57% 99.67% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::65536-98303 94 0.18% 99.86% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::98304-131071 42 0.08% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::131072-163839 10 0.02% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::163840-196607 7 0.01% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::total 51357 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkCompletionTime::samples 50406 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::mean 27093.679324 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::gmean 23240.458219 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::stdev 16758.841159 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::0-32767 28504 56.55% 56.55% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::32768-65535 21034 41.73% 98.28% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::65536-98303 420 0.83% 99.11% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::98304-131071 332 0.66% 99.77% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::131072-163839 37 0.07% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::163840-196607 32 0.06% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::196608-229375 12 0.02% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::total 50406 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walksPending::samples -26472605720 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::mean 1.148605 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::0 3969304628 -14.99% -14.99% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::1 -30473405348 115.11% 100.12% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::2 28081500 -0.11% 100.01% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::3 3146000 -0.01% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::4 137000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::5 114000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::6 8000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::7 8500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::total -26472605720 # Table walker pending requests distribution
+system.cpu3.itb.walker.walkPageSizes::4K 40428 95.69% 95.69% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::2M 1820 4.31% 100.00% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::total 42248 # Table walker page sizes translated
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 59515 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::total 59515 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 42248 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::total 42248 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin::total 101763 # Table walker requests started/completed, data/inst
+system.cpu3.itb.inst_hits 54520119 # ITB inst hits
+system.cpu3.itb.inst_misses 59515 # ITB inst misses
+system.cpu3.itb.read_hits 0 # DTB read hits
+system.cpu3.itb.read_misses 0 # DTB read misses
+system.cpu3.itb.write_hits 0 # DTB write hits
+system.cpu3.itb.write_misses 0 # DTB write misses
+system.cpu3.itb.flush_tlb 1179 # Number of times complete TLB was flushed
+system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu3.itb.flush_tlb_mva_asid 11674 # Number of times TLB was flushed by MVA & ASID
+system.cpu3.itb.flush_tlb_asid 299 # Number of times TLB was flushed by ASID
+system.cpu3.itb.flush_entries 21966 # Number of entries that have been flushed from TLB
+system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu3.itb.perms_faults 118601 # Number of TLB faults due to permissions restrictions
+system.cpu3.itb.read_accesses 0 # DTB read accesses
+system.cpu3.itb.write_accesses 0 # DTB write accesses
+system.cpu3.itb.inst_accesses 54579634 # ITB inst accesses
+system.cpu3.itb.hits 54520119 # DTB hits
+system.cpu3.itb.misses 59515 # DTB misses
+system.cpu3.itb.accesses 54579634 # DTB accesses
+system.cpu3.numCycles 361365292 # number of cpu cycles simulated
+system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu3.fetch.icacheStallCycles 141188803 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 334212277 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 75157877 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 46364225 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 199187397 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 7734395 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.TlbCycles 1397358 # Number of cycles fetch has spent waiting for tlb
+system.cpu3.fetch.MiscStallCycles 6420 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.PendingDrainCycles 2372 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu3.fetch.PendingTrapStallCycles 3033071 # Number of stall cycles due to pending traps
+system.cpu3.fetch.PendingQuiesceStallCycles 90584 # Number of stall cycles due to pending quiesce instructions
+system.cpu3.fetch.IcacheWaitRetryStallCycles 3440 # Number of stall cycles due to full MSHR
+system.cpu3.fetch.CacheLines 54384224 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 2106741 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.ItlbSquashes 23723 # Number of outstanding ITLB misses that were squashed
+system.cpu3.fetch.rateDist::samples 348776447 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.121764 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.363245 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 266236191 76.33% 76.33% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 10517145 3.02% 79.35% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 10460372 3.00% 82.35% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 7763584 2.23% 84.57% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 15658447 4.49% 89.06% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 5090746 1.46% 90.52% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 5553519 1.59% 92.12% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 4863826 1.39% 93.51% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 22632617 6.49% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::total 348776447 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.207983 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 0.924860 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 115165884 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 162148875 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 61184358 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 7206821 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 3068716 # Number of cycles decode is squashing
+system.cpu3.decode.BranchResolved 11212761 # Number of times decode resolved a branch
+system.cpu3.decode.BranchMispred 810030 # Number of times decode detected a branch misprediction
+system.cpu3.decode.DecodedInsts 365054891 # Number of instructions handled by decode
+system.cpu3.decode.SquashedInsts 2491895 # Number of squashed instructions handled by decode
+system.cpu3.rename.SquashCycles 3068716 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 119377384 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 12649358 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 130577518 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles 64081160 # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles 19020412 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 356185546 # Number of instructions processed by rename
+system.cpu3.rename.ROBFullEvents 41963 # Number of times rename has blocked due to ROB full
+system.cpu3.rename.IQFullEvents 1038308 # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents 801382 # Number of times rename has blocked due to LQ full
+system.cpu3.rename.SQFullEvents 8908900 # Number of times rename has blocked due to SQ full
+system.cpu3.rename.FullRegisterEvents 2068 # Number of times there has been no free registers
+system.cpu3.rename.RenamedOperands 339701413 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 543048215 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 420838737 # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups 489590 # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps 283499579 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 56201829 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 7935014 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 6800551 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 39752644 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 57621684 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 48771091 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 7646320 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 8098105 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 338209447 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 7991300 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 336799958 # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued 493625 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined 46981873 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 30279381 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved 194982 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples 348776447 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 0.965661 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.679402 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 218198931 62.56% 62.56% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 53432546 15.32% 77.88% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 24862182 7.13% 85.01% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 17747115 5.09% 90.10% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4 13068769 3.75% 93.85% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 9162782 2.63% 96.47% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 6242831 1.79% 98.26% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 3634597 1.04% 99.30% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8 2426694 0.70% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 348776447 # Number of insts issued each cycle
+system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 1722255 26.20% 26.20% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult 16072 0.24% 26.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv 1128 0.02% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc 1 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 2609788 39.70% 66.16% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 2224178 33.84% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu3.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 228441301 67.83% 67.83% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult 866625 0.26% 68.08% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv 39602 0.01% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 39134 0.01% 68.11% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 60438362 17.94% 86.05% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 46974933 13.95% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::total 336799958 # Type of FU issued
+system.cpu3.iq.rate 0.932021 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 6573422 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.019517 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 1028800637 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 393256983 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 324790914 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads 642773 # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes 320221 # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses 286838 # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses 343029301 # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses 344078 # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads 2684495 # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu3.iew.lsq.thread0.squashedLoads 9539540 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses 13050 # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 400702 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 5115949 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu3.iew.lsq.thread0.rescheduledLoads 2114056 # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked 3866933 # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu3.iew.iewSquashCycles 3068716 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 8569768 # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles 3216654 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts 346278716 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 1046515 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 57621684 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 48771091 # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts 6645619 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents 129030 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents 3038668 # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents 400702 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 1583590 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 1353598 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 2937188 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 332817802 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 59181929 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 3473252 # Number of squashed instructions skipped in execute
+system.cpu3.iew.exec_swp 0 # number of swp insts executed
+system.cpu3.iew.exec_nop 77969 # number of nop insts executed
+system.cpu3.iew.exec_refs 105520536 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 61786884 # Number of branches executed
+system.cpu3.iew.exec_stores 46338607 # Number of stores executed
+system.cpu3.iew.exec_rate 0.921001 # Inst execution rate
+system.cpu3.iew.wb_sent 325791778 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 325077752 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 160558315 # num instructions producing a value
+system.cpu3.iew.wb_consumers 278246243 # num instructions consuming a value
+system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu3.iew.wb_rate 0.899582 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.577037 # average fanout of values written-back
+system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu3.commit.commitSquashedInsts 47005398 # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls 7796318 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts 2618044 # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples 340807461 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean 0.877970 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 1.872285 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 232401746 68.19% 68.19% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 52180181 15.31% 83.50% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 19062195 5.59% 89.10% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 8578726 2.52% 91.61% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 6304961 1.85% 93.46% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 3698650 1.09% 94.55% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 3483571 1.02% 95.57% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 2215848 0.65% 96.22% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8 12881583 3.78% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::total 340807461 # Number of insts commited each cycle
+system.cpu3.commit.committedInsts 254571933 # Number of instructions committed
+system.cpu3.commit.committedOps 299218869 # Number of ops (including micro ops) committed
+system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu3.commit.refs 91737285 # Number of memory references committed
+system.cpu3.commit.loads 48082143 # Number of loads committed
+system.cpu3.commit.membars 2101761 # Number of memory barriers committed
+system.cpu3.commit.branches 56830426 # Number of branches committed
+system.cpu3.commit.fp_insts 274837 # Number of committed floating point instructions.
+system.cpu3.commit.int_insts 275203911 # Number of committed integer instructions.
+system.cpu3.commit.function_calls 7606631 # Number of function calls committed.
+system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu 206755279 69.10% 69.10% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult 663617 0.22% 69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv 29152 0.01% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc 33536 0.01% 69.34% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead 48082143 16.07% 85.41% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite 43655142 14.59% 100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::total 299218869 # Class of committed instruction
+system.cpu3.commit.bw_lim_events 12881583 # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads 672002413 # The number of ROB reads
+system.cpu3.rob.rob_writes 700430084 # The number of ROB writes
+system.cpu3.timesIdled 2364277 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles 12588845 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles 98652153144 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts 254571933 # Number of Instructions Simulated
+system.cpu3.committedOps 299218869 # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi 1.419502 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 1.419502 # CPI: Total CPI of All Threads
+system.cpu3.ipc 0.704473 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 0.704473 # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads 392353216 # number of integer regfile reads
+system.cpu3.int_regfile_writes 232744708 # number of integer regfile writes
+system.cpu3.fp_regfile_reads 564242 # number of floating regfile reads
+system.cpu3.fp_regfile_writes 330472 # number of floating regfile writes
+system.cpu3.cc_regfile_reads 70058550 # number of cc regfile reads
+system.cpu3.cc_regfile_writes 70773135 # number of cc regfile writes
+system.cpu3.misc_regfile_reads 654632577 # number of misc regfile reads
+system.cpu3.misc_regfile_writes 7821457 # number of misc regfile writes
+system.iobus.trans_dist::ReadReq 40271 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40271 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136539 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136539 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122568 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230964 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230964 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353600 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47706 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 353620 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155698 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155706 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334288 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334288 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7492024 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 13118000 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 7492080 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 14862000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 4000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 7299000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 10428000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 33000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 45000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 16991000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 18725000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 175678218 # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy 246351678 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 37744000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 45146000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 35540000 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 48770000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer4.occupancy 80000 # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 115457 # number of replacements
-system.iocache.tags.tagsinuse 10.416552 # Cycle average of tags in use
+system.iocache.tags.replacements 115464 # number of replacements
+system.iocache.tags.tagsinuse 10.421022 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 115480 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 13085993128009 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 5.913060 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 4.503492 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.369566 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.281468 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.651035 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 13087689851509 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.547375 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.873647 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.221711 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.429603 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.651314 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1039641 # Number of tag accesses
-system.iocache.tags.data_accesses 1039641 # Number of data accesses
+system.iocache.tags.tag_accesses 1039695 # Number of tag accesses
+system.iocache.tags.data_accesses 1039695 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8818 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8855 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 8812 # number of demand (read+write) misses
-system.iocache.demand_misses::total 8852 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8818 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8858 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 8812 # number of overall misses
-system.iocache.overall_misses::total 8852 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet 2432000 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide 80359879 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 82791879 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 3987954339 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 3987954339 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet 2432000 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide 80359879 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 82791879 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet 2432000 # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide 80359879 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 82791879 # number of overall miss cycles
+system.iocache.overall_misses::realview.ide 8818 # number of overall misses
+system.iocache.overall_misses::total 8858 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide 66023672 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 66023672 # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide 5601261006 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total 5601261006 # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 66023672 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 66023672 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 66023672 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 66023672 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses)
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system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.785953 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.396740 # mshr miss rate for UpgradeReq accesses
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-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.213975 # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total 0.081595 # mshr miss rate for InvalidateReq accesses
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+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 165311.250675 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 167440.391920 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158585.806160 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 161363.544572 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 162847.532905 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 76733 # Transaction distribution
-system.membus.trans_dist::ReadResp 468089 # Transaction distribution
-system.membus.trans_dist::WriteReq 33644 # Transaction distribution
-system.membus.trans_dist::WriteResp 33644 # Transaction distribution
-system.membus.trans_dist::Writeback 1209847 # Transaction distribution
-system.membus.trans_dist::CleanEvict 210029 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 36410 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 36413 # Transaction distribution
-system.membus.trans_dist::ReadExReq 1013774 # Transaction distribution
-system.membus.trans_dist::ReadExResp 1013774 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 391356 # Transaction distribution
+system.membus.trans_dist::ReadReq 76737 # Transaction distribution
+system.membus.trans_dist::ReadResp 451400 # Transaction distribution
+system.membus.trans_dist::WriteReq 33647 # Transaction distribution
+system.membus.trans_dist::WriteResp 33647 # Transaction distribution
+system.membus.trans_dist::Writeback 1088767 # Transaction distribution
+system.membus.trans_dist::CleanEvict 205338 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 34966 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 34968 # Transaction distribution
+system.membus.trans_dist::ReadExReq 904844 # Transaction distribution
+system.membus.trans_dist::ReadExResp 904844 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 374663 # Transaction distribution
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122568 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 61 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6750 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4261294 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4390673 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 345792 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 345792 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4736465 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155698 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 62 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6756 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3881435 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4010829 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 345611 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 345611 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4356440 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155706 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13500 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 160146208 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 160315602 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7368448 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7368448 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 167684050 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 579 # Total snoops (count)
-system.membus.snoop_fanout::samples 3078821 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13512 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 144353760 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 144523174 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7363392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7363392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 151886566 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 711 # Total snoops (count)
+system.membus.snoop_fanout::samples 2826104 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3078821 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 2826104 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3078821 # Request fanout histogram
-system.membus.reqLayer0.occupancy 45758500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 2826104 # Request fanout histogram
+system.membus.reqLayer0.occupancy 51928000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 2500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 2000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1294500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1759000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 3125844189 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 3236688724 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 2930708426 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 2999492092 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 61033927 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 84543932 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 1510117 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 22871416 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 33644 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 33644 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 8317119 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 16946911 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 45584 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 45593 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 2106266 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 2106266 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 14504828 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 6856794 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 1265720 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 1231984 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 43598497 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 30808593 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 852484 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1760318 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 77019892 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 928472660 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1076191614 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3123312 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6312032 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 2014099618 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 938060 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 51670008 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.040962 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.198203 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 1501925 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 23827607 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 33647 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 33647 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 8029950 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 18099474 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 43761 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 43765 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 1993953 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 1993953 # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq 15783383 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 6542484 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 1272617 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp 1225217 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47433804 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29504905 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 816519 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1737039 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 79492267 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1010303252 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1029626962 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2926248 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6100712 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 2048957174 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 1001590 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 53371149 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.039891 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.195703 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 49553478 95.90% 95.90% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 2116530 4.10% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 51242120 96.01% 96.01% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 2129029 3.99% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 51670008 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 17416968994 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 53371149 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 20695529987 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 316500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 462000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 11880834300 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 15394171442 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 7217033015 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 7879772837 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 275805669 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 290523250 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 649517949 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 715846054 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu2.kern.inst.arm 0 # number of arm instructions executed
-system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.cpu3.kern.inst.arm 0 # number of arm instructions executed
+system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000013] Console: colour dummy device 80x25\r
-[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000015] pid_max: default: 32768 minimum: 301\r
-[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000066] hw perfevents: no hardware support available\r
-[ 1.060050] CPU1: failed to come online\r
-[ 2.080101] CPU2: failed to come online\r
-[ 3.100152] CPU3: failed to come online\r
-[ 3.100153] Brought up 1 CPUs\r
-[ 3.100154] SMP: Total of 1 processors activated.\r
-[ 3.100181] devtmpfs: initialized\r
-[ 3.100715] atomic64_test: passed\r
-[ 3.100742] regulator-dummy: no parameters\r
-[ 3.100963] NET: Registered protocol family 16\r
-[ 3.101057] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.101060] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.101099] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.101101] Serial: AMBA PL011 UART driver\r
-[ 3.101342] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.101409] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.101679] console [ttyAMA0] enabled\r
-[ 3.101713] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.101727] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.101741] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.101754] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.130360] 3V3: 3300 mV \r
-[ 3.130381] vgaarb: loaded\r
-[ 3.130421] SCSI subsystem initialized\r
-[ 3.130490] libata version 3.00 loaded.\r
-[ 3.130570] usbcore: registered new interface driver usbfs\r
+[ 0.000027] Console: colour dummy device 80x25\r
+[ 0.000030] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000032] pid_max: default: 32768 minimum: 301\r
+[ 0.000047] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000048] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000169] hw perfevents: no hardware support available\r
+[ 1.060045] CPU1: failed to come online\r
+[ 2.080096] CPU2: failed to come online\r
+[ 3.100147] CPU3: failed to come online\r
+[ 3.100148] Brought up 1 CPUs\r
+[ 3.100149] SMP: Total of 1 processors activated.\r
+[ 3.100176] devtmpfs: initialized\r
+[ 3.100788] atomic64_test: passed\r
+[ 3.100845] regulator-dummy: no parameters\r
+[ 3.101102] NET: Registered protocol family 16\r
+[ 3.101191] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 3.101195] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 3.101234] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 3.101235] Serial: AMBA PL011 UART driver\r
+[ 3.101357] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 3.101379] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 3.101541] console [ttyAMA0] enabled\r
+[ 3.101668] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 3.101706] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 3.101743] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 3.101777] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 3.130355] 3V3: 3300 mV \r
+[ 3.130376] vgaarb: loaded\r
+[ 3.130417] SCSI subsystem initialized\r
+[ 3.130486] libata version 3.00 loaded.\r
+[ 3.130569] usbcore: registered new interface driver usbfs\r
[ 3.130596] usbcore: registered new interface driver hub\r
[ 3.130650] usbcore: registered new device driver usb\r
-[ 3.130669] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.130677] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.130694] PTP clock support registered\r
-[ 3.130766] Switched to clocksource arch_sys_counter\r
-[ 3.131600] NET: Registered protocol family 2\r
-[ 3.131646] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.131660] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.131666] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.131669] TCP: reno registered\r
-[ 3.131670] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131673] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131687] NET: Registered protocol family 1\r
-[ 3.131717] RPC: Registered named UNIX socket transport module.\r
-[ 3.131718] RPC: Registered udp transport module.\r
-[ 3.131719] RPC: Registered tcp transport module.\r
-[ 3.131720] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.131721] PCI: CLS 0 bytes, default 64\r
-[ 3.131820] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.131862] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.133297] fuse init (API version 7.23)\r
-[ 3.133349] msgmni has been set to 469\r
-[ 3.135215] io scheduler noop registered\r
-[ 3.135250] io scheduler cfq registered (default)\r
-[ 3.135478] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.135480] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.135481] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.135483] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.135484] pci_bus 0000:00: scanning bus\r
-[ 3.135486] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.135488] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.135491] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.135508] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.135510] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.135511] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.135513] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.135515] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.135516] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.135518] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.135536] pci_bus 0000:00: fixups for bus\r
-[ 3.135537] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.135539] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.135543] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.135545] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.135547] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.135549] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.135551] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.135553] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.135554] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.135556] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.135558] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.135559] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.135561] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.135563] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.136019] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.136176] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.136185] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.136198] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.136386] scsi0 : ata_piix\r
-[ 3.136441] scsi1 : ata_piix\r
-[ 3.136483] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.136496] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.136684] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.136696] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.136709] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.136719] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.290771] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.290772] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.290779] ata1.00: configured for UDMA/33\r
-[ 3.290796] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.290857] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.290865] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.290879] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.290880] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.290887] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.290940] sda: sda1\r
-[ 3.291002] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.411060] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.411075] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.411103] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.411114] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.411144] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.411156] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.411274] usbcore: registered new interface driver usb-storage\r
-[ 3.411311] mousedev: PS/2 mouse device common for all mice\r
-[ 3.411407] usbcore: registered new interface driver usbhid\r
-[ 3.411416] usbhid: USB HID core driver\r
-[ 3.411437] TCP: cubic registered\r
-[ 3.411444] NET: Registered protocol family 17\r
-\0[ 3.411630] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.411640] devtmpfs: mounted\r
-[ 3.411648] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+[ 3.130683] pps_core: LinuxPPS API ver. 1 registered\r
+[ 3.130692] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 3.130711] PTP clock support registered\r
+[ 3.130862] Switched to clocksource arch_sys_counter\r
+[ 3.131801] NET: Registered protocol family 2\r
+[ 3.131900] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 3.131914] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 3.131929] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 3.131942] TCP: reno registered\r
+[ 3.131948] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.131960] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.131987] NET: Registered protocol family 1\r
+[ 3.132018] RPC: Registered named UNIX socket transport module.\r
+[ 3.132028] RPC: Registered udp transport module.\r
+[ 3.132035] RPC: Registered tcp transport module.\r
+[ 3.132043] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 3.132054] PCI: CLS 0 bytes, default 64\r
+[ 3.132151] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 3.132209] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 3.133926] fuse init (API version 7.23)\r
+[ 3.133982] msgmni has been set to 469\r
+[ 3.135967] io scheduler noop registered\r
+[ 3.136002] io scheduler cfq registered (default)\r
+[ 3.136279] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 3.136281] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 3.136283] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 3.136284] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 3.136285] pci_bus 0000:00: scanning bus\r
+[ 3.136288] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 3.136290] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 3.136292] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.136309] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 3.136311] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 3.136313] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 3.136315] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 3.136316] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 3.136318] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 3.136320] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.136337] pci_bus 0000:00: fixups for bus\r
+[ 3.136338] pci_bus 0000:00: bus scan returning with max=00\r
+[ 3.136340] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 3.136345] pci 0000:00:00.0: fixup irq: got 33\r
+[ 3.136346] pci 0000:00:00.0: assigning IRQ 33\r
+[ 3.136349] pci 0000:00:01.0: fixup irq: got 34\r
+[ 3.136350] pci 0000:00:01.0: assigning IRQ 34\r
+[ 3.136352] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 3.136354] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 3.136356] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 3.136357] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 3.136359] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 3.136361] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 3.136363] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 3.136364] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 3.136957] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 3.137115] ata_piix 0000:00:01.0: version 2.13\r
+[ 3.137124] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 3.137143] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 3.137321] scsi0 : ata_piix\r
+[ 3.137376] scsi1 : ata_piix\r
+[ 3.137393] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 3.137395] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 3.137475] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 3.137488] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 3.137509] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 3.137522] e1000 0000:00:00.0: enabling bus mastering\r
+[ 3.290865] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 3.290866] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 3.290873] ata1.00: configured for UDMA/33\r
+[ 3.290889] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 3.290951] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 3.290958] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 3.290972] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 3.290974] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 3.290981] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 3.291034] sda: sda1\r
+[ 3.291096] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 3.411154] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 3.411169] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 3.411198] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 3.411208] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 3.411238] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 3.411251] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 3.411375] usbcore: registered new interface driver usb-storage\r
+[ 3.411444] mousedev: PS/2 mouse device common for all mice\r
+[ 3.411624] usbcore: registered new interface driver usbhid\r
+[ 3.411633] usbhid: USB HID core driver\r
+[ 3.411655] TCP: cubic registered\r
+[ 3.411662] NET: Registered protocol family 17\r
+\0[ 3.411877] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 3.411887] devtmpfs: mounted\r
+[ 3.411895] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 3.449130] udevd[607]: starting version 182\r
+[ 3.450115] udevd[607]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 3.543090] random: dd urandom read with 19 bits of entropy available\r
+[ 3.533154] random: dd urandom read with 19 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.660992] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+[ 3.671081] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
projects / gem5.git / commitdiff