Finish explanation

diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
index 95a368306797d25ee5059a3a4e52fd8f70ab9cb8..504f8a0d87f434ffbfeb71688eb0f42b2af624f2 100644 (file)
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc_model.v
@@ -44,6 +44,16 @@ endmodule
 module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
 endmodule
 
+// Boxes used to represent the comb/seq behaviour of DSP48E1
+//   With abc_map.v responsible for disconnecting inputs to
+//   the combinatorial DSP48E1 model by a register (e.g.
+//   disconnecting A when AREG, MREG or PREG is enabled)
+//   this mux captures the existence of a replacement path
+//   between AREG/BREG/CREG/etc. and P/PCOUT.
+//   Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at
+//   the mux at zero time, the combinatorial delay through
+//   these muxes thus represents the clock-to-q delay at
+//   P/PCOUT.
 (* abc_box_id=2100 *)
 module \$__ABC_DSP48E1_MULT_P_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O);
 endmodule
@@ -51,10 +61,6 @@ endmodule
 module \$__ABC_DSP48E1_MULT_PCOUT_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O);
 endmodule
 
-// Box used to represent the comb/seq behaviour of DSP48E1
-//   abc_map.v is responsible for disconnecting inputs to
-//   the combinatorial DSP48E1 model by a register (e.g.
-//   disconnecting A when AREG, MREG or PREG is enabled)
 (* abc_box_id=3000 *)
 module \$__ABC_DSP48E1_MULT (
     output [29:0] ACOUT,

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index bbd38d90cecbad649c6bc23ed6168e46ce50d5c4..e4b1dcd3277b6f82b0b2a99fc6847d6189a14cb4 100644 (file)
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -60,6 +60,16 @@ $__ABC_LUT6 2000 0 7 1
 $__ABC_LUT7 2001 0 8 1
 0 1047 1036 877 812 643 532 478
 
+# Boxes used to represent the comb/seq behaviour of DSP48E1
+#   With abc_map.v responsible for disconnecting inputs to
+#   the combinatorial DSP48E1 model by a register (e.g.
+#   disconnecting A when AREG, MREG or PREG is enabled)
+#   this mux captures the existence of a replacement path
+#   between AREG/BREG/CREG/etc. and P/PCOUT.
+#   Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at
+#   the mux at zero time, the combinatorial delay through
+#   these muxes thus represents the clock-to-q delay at
+#   P/PCOUT.
 $__ABC_DSP48E1_MULT_P_MUX 2100 0 55 48
 # A AD    B    C D    M P                                                                                                Pq
 2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
@@ -110,7 +120,6 @@ $__ABC_DSP48E1_MULT_P_MUX 2100 0 55 48
 2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
 2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
 2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-
 $__ABC_DSP48E1_MULT_PCOUT_MUX 2101 0 55 48
 # A AD    B    C D    M P                                                                                                Pq
 3098 - 2960 1835 - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435