add set[n]bc[r] -- tests broken

diff --git a/openpower/isa/sprset.mdwn b/openpower/isa/sprset.mdwn
index f51cbbb66e372dfe180e768a65191678d1cb3771..7dcefecf8dc3e8dd5ae4f67a6f7b99fd0e674bee 100644 (file)
--- a/openpower/isa/sprset.mdwn
+++ b/openpower/isa/sprset.mdwn
@@ -175,6 +175,62 @@ Special Registers Altered:
 
     None
 
+# Set Boolean Condition
+
+X-Form
+
+* setbc RT,BI
+
+Pseudo-code:
+
+    RT <- (CR[BI] = 1) ? 1 : 0
+
+Special Registers Altered:
+
+    None
+
+# Set Boolean Condition Reverse
+
+X-Form
+
+* setbcr RT,BI
+
+Pseudo-code:
+
+    RT <- (CR[BI] = 1) ? 0 : 1
+
+Special Registers Altered:
+
+    None
+
+# Set Negative Boolean Condition
+
+X-Form
+
+* setnbc RT,BI
+
+Pseudo-code:
+
+    RT <- (CR[BI] = 1) ? -1 : 0
+
+Special Registers Altered:
+
+    None
+
+# Set Negative Boolean Condition Reverse
+
+X-Form
+
+* setnbcr RT,BI
+
+Pseudo-code:
+
+    RT <- (CR[BI] = 1) ? 0 : -1
+
+Special Registers Altered:
+
+    None
+
 <!-- Out of order from the PDF. Page 977 -->
 
 # Move To Machine State Register

diff --git a/openpower/isatables/RM-2P-1S1D.csv b/openpower/isatables/RM-2P-1S1D.csv
index 32df21be0e6619788e8d79f2dfb5a1059d00ce84..b1e2ce6630a36d0d89da15b20e0776a0eb993196 100644 (file)
--- a/openpower/isatables/RM-2P-1S1D.csv
+++ b/openpower/isatables/RM-2P-1S1D.csv
@@ -2,6 +2,10 @@ insn,mode,CONDITIONS,Ptype,Etype,SM,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
 mcrf,NORMAL,,2P,EXTRA3,EN,d:BF,s:BFA,0,0,0,0,0,0,BFA,BF,0
 mfcr/mfocrf,NORMAL,,2P,EXTRA3,EN,d:RT,s:CR,0,0,0,0,0,RT,WHOLE_REG,0,0
 setb,NORMAL,,2P,EXTRA3,EN,d:RT,s:BFA,0,0,0,0,0,RT,BFA,0,0
+setbc,NORMAL,,2P,EXTRA3,EN,d:RT,s:BI,0,0,0,0,0,RT,BI,0,0
+setbcr,NORMAL,,2P,EXTRA3,EN,d:RT,s:BI,0,0,0,0,0,RT,BI,0,0
+setnbc,NORMAL,,2P,EXTRA3,EN,d:RT,s:BI,0,0,0,0,0,RT,BI,0,0
+setnbcr,NORMAL,,2P,EXTRA3,EN,d:RT,s:BI,0,0,0,0,0,RT,BI,0,0
 5/0=ftsqrt,NORMAL,,2P,EXTRA3,EN,d:BF,s:FRB,0,0,0,FRB,0,0,0,BF,0
 22/7=mtfsf,NORMAL,,2P,EXTRA3,EN,d:CR1,s:FRB,0,0,0,FRB,0,0,0,CR1,0
 cmpli,CROP,,2P,EXTRA3,EN,d:BF,s:RA,0,0,RA,0,0,0,0,BF,0

diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text
index 609c6c49df9c9aa5cce255d95b87d756e0cb4117..76227ed5c0c695a47d45c18782ea8e6146934173 100644 (file)
--- a/openpower/isatables/fields.text
+++ b/openpower/isatables/fields.text
@@ -75,6 +75,7 @@
     | PO   |       RT      |     ///     |    RB       |   XO |  / |
     | PO   |       RT      |     ///     |    RB       |   XO | 1  |
     | PO   |       RT      |     ///     |     ///     |   XO |  / |
+    | PO   |       RT      |    BI       |     ///     |   XO |  / |
     | PO   |       RS      |    RA       |    RB       |   XO |Rc  |
     | PO   |       RT      |    RA       |    RB       |   XO |Rc  |
     | PO   |       RS      |    RA       |    RB       |   XO | 1  |

diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv
index de280854c0d91298364a7644b71e14e57f490fcf..c019f40e29c3c22b292e1cd4ab372315dcc50c11 100644 (file)
--- a/openpower/isatables/minor_31.csv
+++ b/openpower/isatables/minor_31.csv
@@ -164,6 +164,10 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b0010111010,LOGICAL,OP_PRTY,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,0,prtyd,X,,,
 0b0010011010,LOGICAL,OP_PRTY,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,0,prtyw,X,,,
 0b0010000000,CR,OP_SETB,NONE,NONE,NONE,RT,BFA,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,setb,X,,,
+0b0110000000,CR,OP_SETBC,NONE,NONE,NONE,RT,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,setbc,X,,,
+0b0110100000,CR,OP_SETBC,NONE,NONE,NONE,RT,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,setbcr,X,,,
+0b0111000000,CR,OP_SETBC,NONE,NONE,NONE,RT,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,setnbc,X,,,
+0b0111100000,CR,OP_SETBC,NONE,NONE,NONE,RT,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,setnbcr,X,,,
 0b0111110010,MMU,OP_TLBIE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,slbia,X,,,
 0b0000011011,SHIFT_ROT,OP_SHL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,sld,X,,,
 0b0000011000,SHIFT_ROT,OP_SHL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,slw,X,,,

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 6ae8d6e0f8a2711c431f3c1c03a80fa647f6582c..ae52cdc84e2ac4b6a0a42baaad51c0406c21b035 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1970,6 +1970,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
                        "mtfpr", "mtfprs",
                        "maddsubrs", "maddrs", "msubrs",
                        "cfuged", "cntlzdm", "cnttzdm", "pdepd", "pextd",
+                       "setbc", "setbcr", "setnbc", "setnbcr",
                        ]:
             illegal = False
             ins_name = dotstrp

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 6ebe1f3b8877020bbfcb614be71f3f052efd8403..db7d1897aeebf983451b12c16ea71f0112126b57 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -811,6 +811,7 @@ _insns = [
     "rldcl", "rldcr", "rldic", "rldicl", "rldicr", "rldimi",
     "rlwimi", "rlwinm",    "rlwnm",
     "setb",
+    "setbc", "setbcr", "setnbc", "setnbcr",
     "setvl",  # https://libre-soc.org/openpower/sv/setvl
     "svindex",  # https://libre-soc.org/openpower/sv/remap
     "svremap",  # https://libre-soc.org/openpower/sv/remap - TEMPORARY
@@ -962,6 +963,7 @@ class MicrOp(Enum):
     OP_CFUGE = 108
     OP_PDEP = 109
     OP_PEXT = 110
+    OP_SETBC = 111
 
 
 class SelType(Enum):

diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py
index 61b97d691d2d293ce90134865a652599b8858f9f..21778ad02d78c4f7ef5b6df93e096f4abbe365ad 100644 (file)
--- a/src/openpower/sv/sv_analysis.py
+++ b/src/openpower/sv/sv_analysis.py
@@ -491,6 +491,9 @@ def extra_classifier(insn_name, value, name, res, regs):
         elif 'mfcr' in insn_name or 'mfocrf' in insn_name:
             res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
             res['1'] = 's:CR'  # CR: Rsrc1_EXTRA3
+        elif regs == ['', '', '', 'RT', 'BI', '']:
+            res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
+            res['1'] = 's:BI'  # BI: Rsrc1_EXTRA3
         elif insn_name == 'setb':
             res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
             res['1'] = 's:BFA'  # BFA: Rsrc1_EXTRA3

diff --git a/src/openpower/test/cr/cr_cases.py b/src/openpower/test/cr/cr_cases.py
index a1346731d45e76009732527f081f29e287657480..1254106224b000b4e6b526568b2485213b5c20f1 100644 (file)
--- a/src/openpower/test/cr/cr_cases.py
+++ b/src/openpower/test/cr/cr_cases.py
@@ -1,10 +1,11 @@
-import unittest
-from openpower.simulator.program import Program
+from nmutil.sim_util import hash_256
+from openpower.test.state import ExpectedState
+from openpower.test.common import TestAccumulatorBase, skip_case
 from openpower.endian import bigendian
-
-from openpower.test.common import TestAccumulatorBase
-from openpower.util import mask_extend
+from openpower.simulator.program import Program
+from openpower.insndb.asm import SVP64Asm
 import random
+import itertools
 
 
 class CRTestCase(TestAccumulatorBase):
@@ -193,3 +194,28 @@ class CRTestCase(TestAccumulatorBase):
         lst = [f"setb 1, 6"]
         cr = random.randint(0, 0x66f6b106)
         self.add_case(Program(lst, bigendian), initial_cr=cr)
+
+    def case_setbc(self):
+        bools = False, True
+        for negate, rev in itertools.product(bools, bools):
+            neg_s = "n" * negate
+            rev_s = "r" * rev
+            mnemonic = f"set{neg_s}bc{rev_s}"
+            prog = Program(list(SVP64Asm([mnemonic + " 3, 10"])), bigendian)
+            for case_idx in range(200):
+                gprs = [0] * 32
+                gprs[3] = 0x123456789ABCDEF
+                cr = hash_256(f"{mnemonic} {case_idx} r4") % 2**32
+                crregs = [(cr >> i) & 0xF for i in reversed(range(0, 32, 4))]
+                e = ExpectedState(pc=4, int_regs=gprs, crregs=crregs)
+                if bool(cr & (1 << 10)) != rev:
+                    if negate:
+                        e.intregs[3] = 2**64 - 1
+                    else:
+                        e.intregs[3] = 1
+                else:
+                    e.intregs[3] = 0
+                with self.subTest(
+                        case_idx=case_idx, CR_in=hex(cr),
+                        expected_RT=hex(e.intregs[3])):
+                    self.add_case(prog, gprs, initial_cr=cr, expected=e)