Add support for the JMP32 class of eBPF instructions.
cpu/ChangeLog
* bpf.cpu (define-cond-jump-insn): Renamed from djci.
(dcji) New version with support for JMP32
gas/ChangeLog
* testsuite/gas/bpf/bpf.exp: Run jump32 tests.
* testsuite/gas/bpf/jump32.s: New file.
* testsuite/gas/bpf/jump32.d: Likewise.
opcodes/ChangeLog
* bpf-desc.c: Regenerate.
* bpf-desc.h: Likewise.
* bpf-opc.c: Regenerate.
* bpf-opc.h: Likewise.
+2020-02-16 David Faust <david.faust@oracle.com>
+
+ * bpf.cpu (define-cond-jump-insn): Renamed from djci.
+ (dcji) New version with support for JMP32
+
2020-02-03 Alan Modra <amodra@gmail.com>
* m32c.cpu (f-dsp-64-s16): Mask before shifting signed value.
(define-normal-insn-enum insn-op-class "eBPF instruction class"
(all-isas) OP_CLASS_ f-op-class
((LD #b000) (LDX #b001) (ST #b010) (STX #b011)
- (ALU #b100) (JMP #b101) (ALU64 #b111)))
+ (ALU #b100) (JMP #b101) (JMP32 #b110) (ALU64 #b111)))
;; For load/store instructions, the 8-bit code field is subdivided in:
;;
;; registers. Therefore, we need to define several variants in both
;; ISAs:
;;
-;; J{eq,gt,ge,lt,le,set,ne,sgt,sge,slt,sle}{i,r}le for the
+;; J{eq,gt,ge,lt,le,set,ne,sgt,sge,slt,sle}[32]{i,r}le for the
;; little-endian ISA.
-;; J{eq,gt,ge,lt,le,set,ne.sgt,sge,slt,sle}{i,r}be for the
+;; J{eq,gt,ge,lt,le,set,ne.sgt,sge,slt,sle}[32]{i,r}be for the
;; big-endian ISA.
-(define-pmacro (dcji x-cond x-op-code x-endian)
+(define-pmacro (define-cond-jump-insn x-cond x-suffix x-op-class x-op-code x-endian)
(begin
- (dni (.sym j x-cond i x-endian)
- (.str j x-cond "i")
+ (dni (.sym j x-cond x-suffix i x-endian)
+ (.str j x-cond x-suffix " i")
((ISA (.sym ebpf x-endian)))
- (.str "j" x-cond " $dst" x-endian ",$imm32,$disp16")
+ (.str "j" x-cond x-suffix " $dst" x-endian ",$imm32,$disp16")
(+ imm32 disp16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
- OP_CLASS_JMP OP_SRC_K (.sym OP_CODE_ x-op-code)) () ())
- (dni (.sym j x-cond r x-endian)
- (.str j x-cond "r")
+ x-op-class OP_SRC_K (.sym OP_CODE_ x-op-code)) () ())
+ (dni (.sym j x-cond x-suffix r x-endian)
+ (.str j x-cond x-suffix " r")
((ISA (.sym ebpf x-endian)))
- (.str "j" x-cond " $dst" x-endian ",$src" x-endian ",$disp16")
+ (.str "j" x-cond x-suffix " $dst" x-endian ",$src" x-endian ",$disp16")
(+ (f-imm32 0) disp16 (.sym src x-endian) (.sym dst x-endian)
- OP_CLASS_JMP OP_SRC_X (.sym OP_CODE_ x-op-code)) () ())))
+ x-op-class OP_SRC_X (.sym OP_CODE_ x-op-code)) () ())))
+
+(define-pmacro (dcji x-cond x-op-code x-endian)
+ (begin
+ (define-cond-jump-insn x-cond "" OP_CLASS_JMP x-op-code x-endian)
+ (define-cond-jump-insn x-cond "32" OP_CLASS_JMP32 x-op-code x-endian)))
(define-pmacro (define-condjump-insns x-endian)
(begin
+2020-02-16 David Faust <david.faust@oracle.com>
+
+ * testsuite/gas/bpf/bpf.exp: Run jump32 tests.
+ * testsuite/gas/bpf/jump32.s: New file.
+ * testsuite/gas/bpf/jump32.d: Likewise.
+
2020-04-08 H.J. Lu <hongjiu.lu@intel.com>
* doc/c-i386.texi: Correct -mlfence-before-indirect-branch=
run_dump_test alu32
run_dump_test mem
run_dump_test jump
+ run_dump_test jump32
run_dump_test call
run_dump_test exit
run_dump_test atomic
--- /dev/null
+#as: --EL
+#objdump: -dr
+#name: eBPF JUMP32 instructions
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 05 00 03 00 00 00 00 00 ja 3
+ 8: 0f 11 00 00 00 00 00 00 add %r1,%r1
+ 10: 16 03 01 00 03 00 00 00 jeq32 %r3,3,1
+ 18: 1e 43 00 00 00 00 00 00 jeq32 %r3,%r4,0
+ 20: 36 03 fd ff 03 00 00 00 jge32 %r3,3,-3
+ 28: 3e 43 fc ff 00 00 00 00 jge32 %r3,%r4,-4
+ 30: a6 03 01 00 03 00 00 00 jlt32 %r3,3,1
+ 38: ae 43 00 00 00 00 00 00 jlt32 %r3,%r4,0
+ 40: b6 03 01 00 03 00 00 00 jle32 %r3,3,1
+ 48: be 43 00 00 00 00 00 00 jle32 %r3,%r4,0
+ 50: 46 03 01 00 03 00 00 00 jset32 %r3,3,1
+ 58: 4e 43 00 00 00 00 00 00 jset32 %r3,%r4,0
+ 60: 56 03 01 00 03 00 00 00 jne32 %r3,3,1
+ 68: 5e 43 00 00 00 00 00 00 jne32 %r3,%r4,0
+ 70: 66 03 01 00 03 00 00 00 jsgt32 %r3,3,1
+ 78: 6e 43 00 00 00 00 00 00 jsgt32 %r3,%r4,0
+ 80: 76 03 01 00 03 00 00 00 jsge32 %r3,3,1
+ 88: 7e 43 00 00 00 00 00 00 jsge32 %r3,%r4,0
+ 90: c6 03 01 00 03 00 00 00 jslt32 %r3,3,1
+ 98: ce 43 00 00 00 00 00 00 jslt32 %r3,%r4,0
+ a0: d6 03 01 00 03 00 00 00 jsle32 %r3,3,1
+ a8: de 43 00 00 00 00 00 00 jsle32 %r3,%r4,0
--- /dev/null
+# Tests for the eBPF JUMP32 instructions
+ .text
+ ja 2f
+ add %r1,%r1
+1: jeq32 %r3,3,2f
+ jeq32 %r3,%r4,2f
+2: jge32 %r3,3,1b
+ jge32 %r3,%r4,1b
+1: jlt32 %r3,3,1f
+ jlt32 %r3,%r4,1f
+1: jle32 %r3,3,1f
+ jle32 %r3,%r4,1f
+1: jset32 %r3,3,1f
+ jset32 %r3,%r4,1f
+1: jne32 %r3,3,1f
+ jne32 %r3,%r4,1f
+1: jsgt32 %r3,3,1f
+ jsgt32 %r3,%r4,1f
+1: jsge32 %r3,3,1f
+ jsge32 %r3,%r4,1f
+1: jslt32 %r3,3,1f
+ jslt32 %r3,%r4,1f
+1: jsle32 %r3,3,1f
+ jsle32 %r3,%r4,1f
+1:
+2020-02-16 David Faust <david.faust@oracle.com>
+
+ * bpf-desc.c: Regenerate.
+ * bpf-desc.h: Likewise.
+ * bpf-opc.c: Regenerate.
+ * bpf-opc.h: Likewise.
+
2020-04-07 Lili Cui <lili.cui@intel.com>
* i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
BPF_INSN_JEQRLE, "jeqrle", "jeq", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
+/* jeq32 $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JEQ32ILE, "jeq32ile", "jeq32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jeq32 $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JEQ32RLE, "jeq32rle", "jeq32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
/* jgt $dstle,$imm32,$disp16 */
{
BPF_INSN_JGTILE, "jgtile", "jgt", 64,
BPF_INSN_JGTRLE, "jgtrle", "jgt", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
+/* jgt32 $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JGT32ILE, "jgt32ile", "jgt32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jgt32 $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JGT32RLE, "jgt32rle", "jgt32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
/* jge $dstle,$imm32,$disp16 */
{
BPF_INSN_JGEILE, "jgeile", "jge", 64,
BPF_INSN_JGERLE, "jgerle", "jge", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
+/* jge32 $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JGE32ILE, "jge32ile", "jge32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jge32 $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JGE32RLE, "jge32rle", "jge32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
/* jlt $dstle,$imm32,$disp16 */
{
BPF_INSN_JLTILE, "jltile", "jlt", 64,
BPF_INSN_JLTRLE, "jltrle", "jlt", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
+/* jlt32 $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JLT32ILE, "jlt32ile", "jlt32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jlt32 $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JLT32RLE, "jlt32rle", "jlt32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
/* jle $dstle,$imm32,$disp16 */
{
BPF_INSN_JLEILE, "jleile", "jle", 64,
BPF_INSN_JLERLE, "jlerle", "jle", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
+/* jle32 $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JLE32ILE, "jle32ile", "jle32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jle32 $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JLE32RLE, "jle32rle", "jle32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
/* jset $dstle,$imm32,$disp16 */
{
BPF_INSN_JSETILE, "jsetile", "jset", 64,
BPF_INSN_JSETRLE, "jsetrle", "jset", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
+/* jset32 $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JSET32ILE, "jset32ile", "jset32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jset32 $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JSET32RLE, "jset32rle", "jset32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
/* jne $dstle,$imm32,$disp16 */
{
BPF_INSN_JNEILE, "jneile", "jne", 64,
BPF_INSN_JNERLE, "jnerle", "jne", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
+/* jne32 $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JNE32ILE, "jne32ile", "jne32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jne32 $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JNE32RLE, "jne32rle", "jne32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
/* jsgt $dstle,$imm32,$disp16 */
{
BPF_INSN_JSGTILE, "jsgtile", "jsgt", 64,
BPF_INSN_JSGTRLE, "jsgtrle", "jsgt", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
+/* jsgt32 $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JSGT32ILE, "jsgt32ile", "jsgt32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jsgt32 $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JSGT32RLE, "jsgt32rle", "jsgt32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
/* jsge $dstle,$imm32,$disp16 */
{
BPF_INSN_JSGEILE, "jsgeile", "jsge", 64,
BPF_INSN_JSGERLE, "jsgerle", "jsge", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
+/* jsge32 $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JSGE32ILE, "jsge32ile", "jsge32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jsge32 $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JSGE32RLE, "jsge32rle", "jsge32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
/* jslt $dstle,$imm32,$disp16 */
{
BPF_INSN_JSLTILE, "jsltile", "jslt", 64,
BPF_INSN_JSLTRLE, "jsltrle", "jslt", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
+/* jslt32 $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JSLT32ILE, "jslt32ile", "jslt32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jslt32 $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JSLT32RLE, "jslt32rle", "jslt32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
/* jsle $dstle,$imm32,$disp16 */
{
BPF_INSN_JSLEILE, "jsleile", "jsle", 64,
BPF_INSN_JSLERLE, "jslerle", "jsle", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
+/* jsle32 $dstle,$imm32,$disp16 */
+ {
+ BPF_INSN_JSLE32ILE, "jsle32ile", "jsle32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* jsle32 $dstle,$srcle,$disp16 */
+ {
+ BPF_INSN_JSLE32RLE, "jsle32rle", "jsle32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
/* jeq $dstbe,$imm32,$disp16 */
{
BPF_INSN_JEQIBE, "jeqibe", "jeq", 64,
BPF_INSN_JEQRBE, "jeqrbe", "jeq", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
+/* jeq32 $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JEQ32IBE, "jeq32ibe", "jeq32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jeq32 $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JEQ32RBE, "jeq32rbe", "jeq32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
/* jgt $dstbe,$imm32,$disp16 */
{
BPF_INSN_JGTIBE, "jgtibe", "jgt", 64,
BPF_INSN_JGTRBE, "jgtrbe", "jgt", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
+/* jgt32 $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JGT32IBE, "jgt32ibe", "jgt32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jgt32 $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JGT32RBE, "jgt32rbe", "jgt32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
/* jge $dstbe,$imm32,$disp16 */
{
BPF_INSN_JGEIBE, "jgeibe", "jge", 64,
BPF_INSN_JGERBE, "jgerbe", "jge", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
+/* jge32 $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JGE32IBE, "jge32ibe", "jge32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jge32 $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JGE32RBE, "jge32rbe", "jge32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
/* jlt $dstbe,$imm32,$disp16 */
{
BPF_INSN_JLTIBE, "jltibe", "jlt", 64,
BPF_INSN_JLTRBE, "jltrbe", "jlt", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
+/* jlt32 $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JLT32IBE, "jlt32ibe", "jlt32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jlt32 $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JLT32RBE, "jlt32rbe", "jlt32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
/* jle $dstbe,$imm32,$disp16 */
{
BPF_INSN_JLEIBE, "jleibe", "jle", 64,
BPF_INSN_JLERBE, "jlerbe", "jle", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
+/* jle32 $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JLE32IBE, "jle32ibe", "jle32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jle32 $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JLE32RBE, "jle32rbe", "jle32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
/* jset $dstbe,$imm32,$disp16 */
{
BPF_INSN_JSETIBE, "jsetibe", "jset", 64,
BPF_INSN_JSETRBE, "jsetrbe", "jset", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
+/* jset32 $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JSET32IBE, "jset32ibe", "jset32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jset32 $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JSET32RBE, "jset32rbe", "jset32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
/* jne $dstbe,$imm32,$disp16 */
{
BPF_INSN_JNEIBE, "jneibe", "jne", 64,
BPF_INSN_JNERBE, "jnerbe", "jne", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
+/* jne32 $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JNE32IBE, "jne32ibe", "jne32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jne32 $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JNE32RBE, "jne32rbe", "jne32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
/* jsgt $dstbe,$imm32,$disp16 */
{
BPF_INSN_JSGTIBE, "jsgtibe", "jsgt", 64,
BPF_INSN_JSGTRBE, "jsgtrbe", "jsgt", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
+/* jsgt32 $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JSGT32IBE, "jsgt32ibe", "jsgt32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jsgt32 $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JSGT32RBE, "jsgt32rbe", "jsgt32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
/* jsge $dstbe,$imm32,$disp16 */
{
BPF_INSN_JSGEIBE, "jsgeibe", "jsge", 64,
BPF_INSN_JSGERBE, "jsgerbe", "jsge", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
+/* jsge32 $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JSGE32IBE, "jsge32ibe", "jsge32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jsge32 $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JSGE32RBE, "jsge32rbe", "jsge32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
/* jslt $dstbe,$imm32,$disp16 */
{
BPF_INSN_JSLTIBE, "jsltibe", "jslt", 64,
BPF_INSN_JSLTRBE, "jsltrbe", "jslt", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
+/* jslt32 $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JSLT32IBE, "jslt32ibe", "jslt32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jslt32 $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JSLT32RBE, "jslt32rbe", "jslt32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
/* jsle $dstbe,$imm32,$disp16 */
{
BPF_INSN_JSLEIBE, "jsleibe", "jsle", 64,
BPF_INSN_JSLERBE, "jslerbe", "jsle", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
+/* jsle32 $dstbe,$imm32,$disp16 */
+ {
+ BPF_INSN_JSLE32IBE, "jsle32ibe", "jsle32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* jsle32 $dstbe,$srcbe,$disp16 */
+ {
+ BPF_INSN_JSLE32RBE, "jsle32rbe", "jsle32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
/* ja $disp16 */
{
BPF_INSN_JA, "ja", "ja", 64,
/* Enum declaration for eBPF instruction class. */
typedef enum insn_op_class {
- OP_CLASS_LD = 0, OP_CLASS_LDX = 1, OP_CLASS_ST = 2, OP_CLASS_STX = 3
- , OP_CLASS_ALU = 4, OP_CLASS_JMP = 5, OP_CLASS_ALU64 = 7
+ OP_CLASS_LD, OP_CLASS_LDX, OP_CLASS_ST, OP_CLASS_STX
+ , OP_CLASS_ALU, OP_CLASS_JMP, OP_CLASS_JMP32, OP_CLASS_ALU64
} INSN_OP_CLASS;
/* Enum declaration for eBPF load/store instruction modes. */
{ { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
& ifmt_jeqrle, { 0x1d }
},
+/* jeq32 $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0x16 }
+ },
+/* jeq32 $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0x1e }
+ },
/* jgt $dstle,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
& ifmt_jeqrle, { 0x2d }
},
+/* jgt32 $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0x26 }
+ },
+/* jgt32 $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0x2e }
+ },
/* jge $dstle,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
& ifmt_jeqrle, { 0x3d }
},
+/* jge32 $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0x36 }
+ },
+/* jge32 $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0x3e }
+ },
/* jlt $dstle,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
& ifmt_jeqrle, { 0xad }
},
+/* jlt32 $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0xa6 }
+ },
+/* jlt32 $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0xae }
+ },
/* jle $dstle,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
& ifmt_jeqrle, { 0xbd }
},
+/* jle32 $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0xb6 }
+ },
+/* jle32 $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0xbe }
+ },
/* jset $dstle,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
& ifmt_jeqrle, { 0x4d }
},
+/* jset32 $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0x46 }
+ },
+/* jset32 $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0x4e }
+ },
/* jne $dstle,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
& ifmt_jeqrle, { 0x5d }
},
+/* jne32 $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0x56 }
+ },
+/* jne32 $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0x5e }
+ },
/* jsgt $dstle,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
& ifmt_jeqrle, { 0x6d }
},
+/* jsgt32 $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0x66 }
+ },
+/* jsgt32 $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0x6e }
+ },
/* jsge $dstle,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
& ifmt_jeqrle, { 0x7d }
},
+/* jsge32 $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0x76 }
+ },
+/* jsge32 $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0x7e }
+ },
/* jslt $dstle,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
& ifmt_jeqrle, { 0xcd }
},
+/* jslt32 $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0xc6 }
+ },
+/* jslt32 $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0xce }
+ },
/* jsle $dstle,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
& ifmt_jeqrle, { 0xdd }
},
+/* jsle32 $dstle,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqile, { 0xd6 }
+ },
+/* jsle32 $dstle,$srcle,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrle, { 0xde }
+ },
/* jeq $dstbe,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
& ifmt_jeqrbe, { 0x1d }
},
+/* jeq32 $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0x16 }
+ },
+/* jeq32 $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0x1e }
+ },
/* jgt $dstbe,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
& ifmt_jeqrbe, { 0x2d }
},
+/* jgt32 $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0x26 }
+ },
+/* jgt32 $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0x2e }
+ },
/* jge $dstbe,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
& ifmt_jeqrbe, { 0x3d }
},
+/* jge32 $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0x36 }
+ },
+/* jge32 $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0x3e }
+ },
/* jlt $dstbe,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
& ifmt_jeqrbe, { 0xad }
},
+/* jlt32 $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0xa6 }
+ },
+/* jlt32 $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0xae }
+ },
/* jle $dstbe,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
& ifmt_jeqrbe, { 0xbd }
},
+/* jle32 $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0xb6 }
+ },
+/* jle32 $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0xbe }
+ },
/* jset $dstbe,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
& ifmt_jeqrbe, { 0x4d }
},
+/* jset32 $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0x46 }
+ },
+/* jset32 $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0x4e }
+ },
/* jne $dstbe,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
& ifmt_jeqrbe, { 0x5d }
},
+/* jne32 $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0x56 }
+ },
+/* jne32 $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0x5e }
+ },
/* jsgt $dstbe,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
& ifmt_jeqrbe, { 0x6d }
},
+/* jsgt32 $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0x66 }
+ },
+/* jsgt32 $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0x6e }
+ },
/* jsge $dstbe,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
& ifmt_jeqrbe, { 0x7d }
},
+/* jsge32 $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0x76 }
+ },
+/* jsge32 $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0x7e }
+ },
/* jslt $dstbe,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
& ifmt_jeqrbe, { 0xcd }
},
+/* jslt32 $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0xc6 }
+ },
+/* jslt32 $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0xce }
+ },
/* jsle $dstbe,$imm32,$disp16 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
& ifmt_jeqrbe, { 0xdd }
},
+/* jsle32 $dstbe,$imm32,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
+ & ifmt_jeqibe, { 0xd6 }
+ },
+/* jsle32 $dstbe,$srcbe,$disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
+ & ifmt_jeqrbe, { 0xde }
+ },
/* ja $disp16 */
{
{ 0, 0, 0, 0 },
, BPF_INSN_STXHBE, BPF_INSN_STXBBE, BPF_INSN_STXDWBE, BPF_INSN_STBLE
, BPF_INSN_STHLE, BPF_INSN_STWLE, BPF_INSN_STDWLE, BPF_INSN_STBBE
, BPF_INSN_STHBE, BPF_INSN_STWBE, BPF_INSN_STDWBE, BPF_INSN_JEQILE
- , BPF_INSN_JEQRLE, BPF_INSN_JGTILE, BPF_INSN_JGTRLE, BPF_INSN_JGEILE
- , BPF_INSN_JGERLE, BPF_INSN_JLTILE, BPF_INSN_JLTRLE, BPF_INSN_JLEILE
- , BPF_INSN_JLERLE, BPF_INSN_JSETILE, BPF_INSN_JSETRLE, BPF_INSN_JNEILE
- , BPF_INSN_JNERLE, BPF_INSN_JSGTILE, BPF_INSN_JSGTRLE, BPF_INSN_JSGEILE
- , BPF_INSN_JSGERLE, BPF_INSN_JSLTILE, BPF_INSN_JSLTRLE, BPF_INSN_JSLEILE
- , BPF_INSN_JSLERLE, BPF_INSN_JEQIBE, BPF_INSN_JEQRBE, BPF_INSN_JGTIBE
- , BPF_INSN_JGTRBE, BPF_INSN_JGEIBE, BPF_INSN_JGERBE, BPF_INSN_JLTIBE
- , BPF_INSN_JLTRBE, BPF_INSN_JLEIBE, BPF_INSN_JLERBE, BPF_INSN_JSETIBE
- , BPF_INSN_JSETRBE, BPF_INSN_JNEIBE, BPF_INSN_JNERBE, BPF_INSN_JSGTIBE
- , BPF_INSN_JSGTRBE, BPF_INSN_JSGEIBE, BPF_INSN_JSGERBE, BPF_INSN_JSLTIBE
- , BPF_INSN_JSLTRBE, BPF_INSN_JSLEIBE, BPF_INSN_JSLERBE, BPF_INSN_JA
+ , BPF_INSN_JEQRLE, BPF_INSN_JEQ32ILE, BPF_INSN_JEQ32RLE, BPF_INSN_JGTILE
+ , BPF_INSN_JGTRLE, BPF_INSN_JGT32ILE, BPF_INSN_JGT32RLE, BPF_INSN_JGEILE
+ , BPF_INSN_JGERLE, BPF_INSN_JGE32ILE, BPF_INSN_JGE32RLE, BPF_INSN_JLTILE
+ , BPF_INSN_JLTRLE, BPF_INSN_JLT32ILE, BPF_INSN_JLT32RLE, BPF_INSN_JLEILE
+ , BPF_INSN_JLERLE, BPF_INSN_JLE32ILE, BPF_INSN_JLE32RLE, BPF_INSN_JSETILE
+ , BPF_INSN_JSETRLE, BPF_INSN_JSET32ILE, BPF_INSN_JSET32RLE, BPF_INSN_JNEILE
+ , BPF_INSN_JNERLE, BPF_INSN_JNE32ILE, BPF_INSN_JNE32RLE, BPF_INSN_JSGTILE
+ , BPF_INSN_JSGTRLE, BPF_INSN_JSGT32ILE, BPF_INSN_JSGT32RLE, BPF_INSN_JSGEILE
+ , BPF_INSN_JSGERLE, BPF_INSN_JSGE32ILE, BPF_INSN_JSGE32RLE, BPF_INSN_JSLTILE
+ , BPF_INSN_JSLTRLE, BPF_INSN_JSLT32ILE, BPF_INSN_JSLT32RLE, BPF_INSN_JSLEILE
+ , BPF_INSN_JSLERLE, BPF_INSN_JSLE32ILE, BPF_INSN_JSLE32RLE, BPF_INSN_JEQIBE
+ , BPF_INSN_JEQRBE, BPF_INSN_JEQ32IBE, BPF_INSN_JEQ32RBE, BPF_INSN_JGTIBE
+ , BPF_INSN_JGTRBE, BPF_INSN_JGT32IBE, BPF_INSN_JGT32RBE, BPF_INSN_JGEIBE
+ , BPF_INSN_JGERBE, BPF_INSN_JGE32IBE, BPF_INSN_JGE32RBE, BPF_INSN_JLTIBE
+ , BPF_INSN_JLTRBE, BPF_INSN_JLT32IBE, BPF_INSN_JLT32RBE, BPF_INSN_JLEIBE
+ , BPF_INSN_JLERBE, BPF_INSN_JLE32IBE, BPF_INSN_JLE32RBE, BPF_INSN_JSETIBE
+ , BPF_INSN_JSETRBE, BPF_INSN_JSET32IBE, BPF_INSN_JSET32RBE, BPF_INSN_JNEIBE
+ , BPF_INSN_JNERBE, BPF_INSN_JNE32IBE, BPF_INSN_JNE32RBE, BPF_INSN_JSGTIBE
+ , BPF_INSN_JSGTRBE, BPF_INSN_JSGT32IBE, BPF_INSN_JSGT32RBE, BPF_INSN_JSGEIBE
+ , BPF_INSN_JSGERBE, BPF_INSN_JSGE32IBE, BPF_INSN_JSGE32RBE, BPF_INSN_JSLTIBE
+ , BPF_INSN_JSLTRBE, BPF_INSN_JSLT32IBE, BPF_INSN_JSLT32RBE, BPF_INSN_JSLEIBE
+ , BPF_INSN_JSLERBE, BPF_INSN_JSLE32IBE, BPF_INSN_JSLE32RBE, BPF_INSN_JA
, BPF_INSN_CALL, BPF_INSN_EXIT, BPF_INSN_XADDDWLE, BPF_INSN_XADDWLE
, BPF_INSN_XADDDWBE, BPF_INSN_XADDWBE
} CGEN_INSN_TYPE;
projects / binutils-gdb.git / commitdiff