misoclib/soc: add _integrated_ to cpu options to avoid confusion

diff --git a/make.py b/make.py
index 3ec4cee0d5157dbefab3a1343150d5c63a228b3a..4253dc1b6d087a055b56abec1fc2a707a1ff982b 100755 (executable)
--- a/make.py
+++ b/make.py
@@ -122,9 +122,9 @@ CPU type:  {}
                actions["build-bios"] = True
                if not actions["load-bitstream"]:
                        actions["flash-bitstream"] = True
-               if not soc.with_rom:
+               if not soc.with_integrated_rom:
                        actions["flash-bios"] = True
-       if actions["build-bitstream"] and soc.with_rom:
+       if actions["build-bitstream"] and soc.with_integrated_rom:
                actions["build-bios"] = True
        if actions["build-bios"]:
                actions["build-headers"] = True
@@ -173,7 +173,7 @@ CPU type:  {}
                        raise OSError("BIOS build failed")
 
        if actions["build-bitstream"]:
-               if soc.with_rom:
+               if soc.with_integrated_rom:
                        with open(soc.cpu_boot_file, "rb") as boot_file:
                                boot_data = []
                                while True:

diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py
index b22d4cfa938df6edd20b18ae80ae4451d9bb70e2..80b26d42503ff894d83ded5997cd02bc11e9f6df 100644 (file)
--- a/misoclib/soc/__init__.py
+++ b/misoclib/soc/__init__.py
@@ -37,9 +37,9 @@ class SoC(Module):
        def __init__(self, platform, clk_freq, cpu_or_bridge=None,
                                with_cpu=True, cpu_type="lm32", cpu_reset_address=0x00000000,
                                                           cpu_boot_file="software/bios/bios.bin",
-                               with_rom=False, rom_size=0x8000,
-                               with_sram=True, sram_size=4096,
-                               with_main_ram=False, main_ram_size=64*1024,
+                               with_integrated_rom=False, rom_size=0x8000,
+                               with_integrated_sram=True, sram_size=4096,
+                               with_integrated_main_ram=False, main_ram_size=64*1024,
                                with_csr=True, csr_data_width=8, csr_address_width=14,
                                with_uart=True, uart_baudrate=115200,
                                with_identifier=True,
@@ -50,19 +50,19 @@ class SoC(Module):
 
                self.with_cpu = with_cpu
                self.cpu_type = cpu_type
-               if with_rom:
+               if with_integrated_rom:
                        self.cpu_reset_address = 0
                else:
                        self.cpu_reset_address = cpu_reset_address
                self.cpu_boot_file = cpu_boot_file
 
-               self.with_rom = with_rom
+               self.with_integrated_rom = with_integrated_rom
                self.rom_size = rom_size
 
-               self.with_sram = with_sram
+               self.with_integrated_sram = with_integrated_sram
                self.sram_size = sram_size
 
-               self.with_main_ram = with_main_ram
+               self.with_integrated_main_ram = with_integrated_main_ram
                self.main_ram_size = main_ram_size
 
                self.with_uart = with_uart
@@ -90,16 +90,16 @@ class SoC(Module):
                        self.cpu_or_bridge = self.cpu
                        self._wb_masters += [self.cpu.ibus, self.cpu.dbus]
 
-                       if with_rom:
+                       if with_integrated_rom:
                                self.submodules.rom = wishbone.SRAM(rom_size, read_only=True)
                                self.register_rom(self.rom.bus, rom_size)
 
-                       if with_sram:
+                       if with_integrated_sram:
                                self.submodules.sram = wishbone.SRAM(sram_size)
                                self.register_mem("sram", self.mem_map["sram"], self.sram.bus, sram_size)
 
                        # Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
-                       if with_main_ram:
+                       if with_integrated_main_ram:
                                self.submodules.main_ram = wishbone.SRAM(main_ram_size)
                                self.register_mem("sdram", self.mem_map["sdram"], self.main_ram.bus, main_ram_size)
 

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index 82725b65b50be9c69a613aa10234174e25a6c8f6..5ead08d6bf949c7cb4c3ee577e7b896c7adbd513 100644 (file)
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -80,7 +80,7 @@ class SDRAMSoC(SoC):
                                raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
 
        def do_finalize(self):
-               if not self.with_main_ram:
+               if not self.with_integrated_main_ram:
                        if not self._sdram_phy_registered:
                                raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
                SoC.do_finalize(self)

diff --git a/targets/de0nano.py b/targets/de0nano.py
index d98468e3b8bfcb71655ace1898fc10b060af0afc..eb124066d90ad83583eada39c494ff0f650bf0a5 100644 (file)
--- a/targets/de0nano.py
+++ b/targets/de0nano.py
@@ -85,12 +85,12 @@ class BaseSoC(SDRAMSoC):
        def __init__(self, platform, **kwargs):
                SDRAMSoC.__init__(self, platform,
                        clk_freq=100*1000000,
-                       with_rom=True,
+                       with_integrated_rom=True,
                        **kwargs)
 
                self.submodules.crg = _CRG(platform)
 
-               if not self.with_main_ram:
+               if not self.with_integrated_main_ram:
                        sdram_module = IS42S16160(self.clk_freq)
                        sdram_controller_settings = sdram.ControllerSettings(
                                req_queue_size=8,

diff --git a/targets/kc705.py b/targets/kc705.py
index db6d483427580a94bf0a64093208bd4136defa4a..e179ddc80f3779616f5953d400611a1030fe58ec 100644 (file)
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -83,7 +83,7 @@ class BaseSoC(SDRAMSoC):
 
                self.submodules.crg = _CRG(platform)
 
-               if not self.with_main_ram:
+               if not self.with_integrated_main_ram:
                        sdram_modules = MT8JTF12864(self.clk_freq)
                        sdram_controller_settings = sdram.ControllerSettings(
                                req_queue_size=8,
@@ -103,7 +103,7 @@ class BaseSoC(SDRAMSoC):
                self.flash_boot_address = 0xb00000
 
                # If not in ROM, BIOS is in SPI flash
-               if not self.with_rom:
+               if not self.with_integrated_rom:
                        self.register_rom(self.spiflash.bus)
 
 class MiniSoC(BaseSoC):

diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index da8c99d6660788e160e00f63e7fb665f9532e7a2..c338ef508cd8799922c4d9f7c312cf89080dcdf5 100644 (file)
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -41,7 +41,7 @@ class BaseSoC(SDRAMSoC):
 
                self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
 
-               if not self.with_main_ram:
+               if not self.with_integrated_main_ram:
                        sdram_modules = MT46V32M16(self.clk_freq)
                        sdram_controller_settings =  sdram.ControllerSettings(
                                req_queue_size=8,
@@ -64,7 +64,7 @@ class BaseSoC(SDRAMSoC):
                self.flash_boot_address = 0x001a0000
 
                # If not in ROM, BIOS is in // NOR flash
-               if not self.with_rom:
+               if not self.with_integrated_rom:
                        self.register_rom(self.norflash.bus)
 
 

diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index 159869924d99bbc54df1e14a68e83a9cda485899..eb657de115cf8705fc697b86e4487ccf58b15e63 100644 (file)
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
@@ -91,14 +91,14 @@ class BaseSoC(SDRAMSoC):
 
        def __init__(self, platform, **kwargs):
                clk_freq = 75*1000*1000
-               if not kwargs.get("with_rom"):
+               if not kwargs.get("with_integrated_rom"):
                        kwargs["rom_size"] = 0x1000000 # 128 Mb
                SDRAMSoC.__init__(self, platform, clk_freq,
                                        cpu_reset_address=0x170000, **kwargs) # 1.5 MB
 
                self.submodules.crg = _CRG(platform, clk_freq)
 
-               if not self.with_main_ram:
+               if not self.with_integrated_main_ram:
                        sdram_module = MT46H32M16(self.clk_freq)
                        sdram_controller_settings = sdram.ControllerSettings(
                                req_queue_size=8,
@@ -119,7 +119,7 @@ class BaseSoC(SDRAMSoC):
 
                self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=10, div=4)
                # If not in ROM, BIOS is in SPI flash
-               if not self.with_rom:
+               if not self.with_integrated_rom:
                        self.flash_boot_address = 0x180000
                        self.register_rom(self.spiflash.bus)
 

diff --git a/targets/ppro.py b/targets/ppro.py
index d69b9e28bd580ff8c17fa5ef1d798fe889fe401b..0dac6b5062effcbcbd260a7cf15bbb8bc0b86cb8 100644 (file)
--- a/targets/ppro.py
+++ b/targets/ppro.py
@@ -74,7 +74,7 @@ class BaseSoC(SDRAMSoC):
 
                self.submodules.crg = _CRG(platform, clk_freq)
 
-               if not self.with_main_ram:
+               if not self.with_integrated_main_ram:
                        sdram_module = MT48LC4M16(clk_freq)
                        sdram_controller_settings = sdram.ControllerSettings(
                                req_queue_size=8,
@@ -89,7 +89,7 @@ class BaseSoC(SDRAMSoC):
                self.flash_boot_address = 0x70000
 
                # If not in ROM, BIOS is in SPI flash
-               if not self.with_rom:
+               if not self.with_integrated_rom:
                        self.register_rom(self.spiflash.bus)
 
 default_subtarget = BaseSoC

diff --git a/targets/simple.py b/targets/simple.py
index 7d16171184119cb6b9a03a00f07448b9be783733..24fdc87b007145639432d1d6942e25092d62fa24 100644 (file)
--- a/targets/simple.py
+++ b/targets/simple.py
@@ -10,8 +10,8 @@ class BaseSoC(SoC):
        def __init__(self, platform, **kwargs):
                SoC.__init__(self, platform,
                        clk_freq=int((1/(platform.default_clk_period))*1000000000),
-                       with_rom=True,
-                       with_main_ram=True, main_ram_size=16*1024,
+                       with_integrated_rom=True,
+                       with_integrated_main_ram=True, main_ram_size=16*1024,
                        **kwargs)
                self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 

diff --git a/targets/versa.py b/targets/versa.py
index c0fe4714abe3c7efccb41cad20163a17fc5149b8..334a5f2ff2ca243283f294eb35a93db794520256 100644 (file)
--- a/targets/versa.py
+++ b/targets/versa.py
@@ -9,7 +9,7 @@ class BaseSoC(SoC):
        def __init__(self, platform, **kwargs):
                SoC.__init__(self, platform,
                        clk_freq=100*1000000,
-                       with_rom=True,
+                       with_integrated_rom=True,
                        **kwargs)
                self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("rst_n"))
                self.comb += platform.request("user_led", 0).eq(ResetSignal())