radv: replace si_emit_wait_fence() with radv_cp_wait_mem()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 6510a5c442555bd61f407e38e9b7b2f768036c63..de67a8a363676fddc86328ca9b7aee78b7c17092 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4406,7 +4406,7 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer,
 
                MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
 
-               si_emit_wait_fence(cs, va, 1, 0xffffffff);
+               radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
                assert(cmd_buffer->cs->cdw <= cdw_max);
        }
 

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 253e6455604e750638180335cb8ee35612127383..1628be10022c98f0d89cfe1e4e6c1261c745097e 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1143,9 +1143,8 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
                                uint32_t new_fence,
                                uint64_t gfx9_eop_bug_va);
 
-void si_emit_wait_fence(struct radeon_cmdbuf *cs,
-                       uint64_t va, uint32_t ref,
-                       uint32_t mask);
+void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
+                     uint32_t ref, uint32_t mask);
 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
                            enum chip_class chip_class,
                            uint32_t *fence_ptr, uint64_t va,

diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 87a9ddf899301d81217c3ffc57c08434d593404c..e5fed673d160b0cb06f1de4346c6074bbeac65ac 100644 (file)
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -1309,7 +1309,8 @@ void radv_CmdCopyQueryPoolResults(
                                uint64_t avail_va = va + pool->availability_offset + 4 * query;
 
                                /* This waits on the ME. All copies below are done on the ME */
-                               si_emit_wait_fence(cs, avail_va, 1, 0xffffffff);
+                               radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL,
+                                                avail_va, 1, 0xffffffff);
                        }
                }
                radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.pipeline_statistics_query_pipeline,

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 9b5ebb29d612a859740a4d865a5626dccc4a7b7f..be37191306976c7a72a7496989cc69a9879a0bfb 100644 (file)
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -725,12 +725,15 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
 }
 
 void
-si_emit_wait_fence(struct radeon_cmdbuf *cs,
-                  uint64_t va, uint32_t ref,
-                  uint32_t mask)
+radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
+                uint32_t ref, uint32_t mask)
 {
+       assert(op == WAIT_REG_MEM_EQUAL ||
+              op == WAIT_REG_MEM_NOT_EQUAL ||
+              op == WAIT_REG_MEM_GREATER_OR_EQUAL);
+
        radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
-       radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
+       radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
        radeon_emit(cs, va);
        radeon_emit(cs, va >> 32);
        radeon_emit(cs, ref); /* reference value */
@@ -875,7 +878,8 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
                                           EOP_DATA_SEL_VALUE_32BIT,
                                           flush_va, old_fence, *flush_cnt,
                                           gfx9_eop_bug_va);
-               si_emit_wait_fence(cs, flush_va, *flush_cnt, 0xffffffff);
+               radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
+                                *flush_cnt, 0xffffffff);
        }
 
        /* VGT state sync */