li x6, pred; \
\
SET_SV_MVL( 2); \
- SET_SV_CSR( 1, 3, SV_W_32BIT, 3, 1); \
+ SET_SV_CSR( 1, 3, SV_W_8BIT, 3, 1); \
SET_SV_PRED_CSR( 1, 3, zero, inv, 6, 0); \
SET_SV_VL( 2); \
SET_SV_SUBVL( 2); \
\
addi x3, x3, 1; \
\
+ SET_SV_SUBVL( 1); \
CLR_SV_CSRS(); \
SET_SV_VL( 1); \
SET_SV_MVL( 1); \
- SET_SV_SUBVL( 1); \
\
TEST_SV_IMM( x2, 1001); \
TEST_SV_IMM( x3, expect1); \
RVTEST_CODE_BEGIN # Start of test code.
# no zeroing, no inversion
-/*
- SV_PREDICATION_TEST( 0x1, 0, 0, 0x4200000043, 0x4300000044 )
+ SV_PREDICATION_TEST( 0x1, 0, 0, 0x41424445, 0 )
+ SV_PREDICATION_TEST( 0x2, 0, 0, 0x42434344, 0 )
+ SV_PREDICATION_TEST( 0x3, 0, 0, 0x42434445, 0 )
+ SV_PREDICATION_TEST( 0x0, 0, 0, 0x41424344, 0 )
- SV_PREDICATION_TEST( 0x2, 0, 0, 41, 43 )
-*/
- //SV_PREDICATION_TEST( 0x3, 0, 0, 0x4200000043, 0x4400000045 )
- SV_PREDICATION_TEST( 0x0, 0, 0, 0x4100000042, 0x4300000044 )
-/*
# zeroing, no inversion
- SV_PREDICATION_TEST( 0x1, 0, 1, 42, 0 )
- SV_PREDICATION_TEST( 0x2, 0, 1, 0, 43 )
- SV_PREDICATION_TEST( 0x3, 0, 1, 42, 43 )
- SV_PREDICATION_TEST( 0x0, 0, 1, 0, 0 )
+ SV_PREDICATION_TEST( 0x1, 0, 1, 0x00004445, 0 )
+ SV_PREDICATION_TEST( 0x2, 0, 1, 0x42430000, 0 )
+ SV_PREDICATION_TEST( 0x3, 0, 1, 0x42434445, 0 )
+ SV_PREDICATION_TEST( 0x0, 0, 1, 0x00000000, 0 )
+/*
# no zeroing, inversion
SV_PREDICATION_TEST( 0x2, 1, 0, 42, 42 )
SV_PREDICATION_TEST( 0x1, 1, 0, 41, 43 )
.align 3
testdata:
.dword 1001
- .dword 0x4100000042
- .dword 0x4300000044
+ .dword 0x41424344
+ .dword 0x00000000
.dword 1002
# Output data section.