adffs test update (equiv_opt -multiclock). div_mod test fix

diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v
index 93c8bf52c75c87ba9282d58eb785ef20458ad58e..05e68caf7e91a6d02759be09648055a44b26025f 100644 (file)
--- a/tests/ecp5/adffs.v
+++ b/tests/ecp5/adffs.v
@@ -22,30 +22,26 @@ module adffn
             q <= d;
 endmodule
 
-module dffsr
+module dffs
     ( input d, clk, pre, clr, output reg q );
     initial begin
       q = 0;
     end
-       always @( posedge clk, posedge pre, posedge clr )
-               if ( clr )
-                       q <= 1'b0;
-               else if ( pre )
+       always @( posedge clk )
+               if ( pre )
                        q <= 1'b1;
                else
             q <= d;
 endmodule
 
-module ndffnsnr
+module ndffnr
     ( input d, clk, pre, clr, output reg q );
     initial begin
       q = 0;
     end
-       always @( negedge clk, negedge pre, negedge clr )
+       always @( negedge clk )
                if ( !clr )
                        q <= 1'b0;
-               else if ( !pre )
-                       q <= 1'b1;
                else
             q <= d;
 endmodule
@@ -58,7 +54,7 @@ input a,
 output b,b1,b2,b3
 );
 
-dffsr u_dffsr (
+dffs u_dffs (
         .clk (clk ),
         .clr (clr),
         .pre (pre),
@@ -66,7 +62,7 @@ dffsr u_dffsr (
         .q (b )
     );
 
-ndffnsnr u_ndffnsnr (
+ndffnr u_ndffnr (
         .clk (clk ),
         .clr (clr),
         .pre (pre),

diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys
index 7ec2b0114df55f412edf30f80d67a94d5bd10532..fc1363a3251178d8d33605ed11d27c3189e19d28 100644 (file)
--- a/tests/ecp5/adffs.ys
+++ b/tests/ecp5/adffs.ys
@@ -1,10 +1,9 @@
 read_verilog adffs.v
 proc
-async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
 flatten
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+equiv_opt -multiclock -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 4 t:TRELLIS_FF
-select -assert-count 7 t:LUT4
+select -assert-count 3 t:LUT4
 select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D

diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys
index fb13be5d59b67cc8cddabb95279f1b98858f9172..9efb00701b906fbb74474c5883840bb9b161dd01 100644 (file)
--- a/tests/ecp5/div_mod.ys
+++ b/tests/ecp5/div_mod.ys
@@ -6,7 +6,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd top # Constrain all select calls below inside the top module
 
 select -assert-count 28 t:CCU2C
-select -assert-count 48 t:L6MUX21
-select -assert-count 194 t:LUT4
-select -assert-count 84 t:PFUMX
+select -assert-count 26 t:L6MUX21
+select -assert-count 138 t:LUT4
+select -assert-count 60 t:PFUMX
 select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D