move more possible logic outside of fsms (to reduce ressource usage)

diff --git a/liteeth/core/arp.py b/liteeth/core/arp.py
index c223d8044d620b5bdbf88443ab0e933af5de7f41..d7fd26deccea1ade8f62e9da7b6ed1ee2fab304d 100644 (file)
--- a/liteeth/core/arp.py
+++ b/liteeth/core/arp.py
@@ -47,6 +47,8 @@ class LiteEthARPTX(Module):
                        )
                )
                self.comb += [
+                       source.sop.eq(counter.value == 0),
+                       source.eop.eq(counter.value == max(arp_header_len, eth_min_len)-1),
                        source.hwtype.eq(arp_hwtype_ethernet),
                        source.proto.eq(arp_proto_ip),
                        source.hwsize.eq(6),
@@ -65,8 +67,6 @@ class LiteEthARPTX(Module):
                ]
                fsm.act("SEND",
                        source.stb.eq(1),
-                       source.sop.eq(counter.value == 0),
-                       source.eop.eq(counter.value == max(arp_header_len, eth_min_len)-1),
                        Record.connect(packetizer.source, self.source),
                        self.source.target_mac.eq(source.target_mac),
                        self.source.sender_mac.eq(mac_address),

diff --git a/liteeth/core/ip.py b/liteeth/core/ip.py
index e0bde4b8e96a4986cab7fb596d422b97d3111ce1..04be1ce7c7f4c5224b49b5f0d0fffb86881736b3 100644 (file)
--- a/liteeth/core/ip.py
+++ b/liteeth/core/ip.py
@@ -80,9 +80,9 @@ class LiteEthIPTX(Module):
                                NextState("SEND_MAC_ADDRESS_REQUEST")
                        )
                )
+               self.comb += arp_table.request.ip_address.eq(self.sink.ip_address)
                fsm.act("SEND_MAC_ADDRESS_REQUEST",
                        arp_table.request.stb.eq(1),
-                       arp_table.request.ip_address.eq(self.sink.ip_address),
                        If(arp_table.request.stb & arp_table.request.ack,
                                NextState("WAIT_MAC_ADDRESS_RESPONSE")
                        )
@@ -152,24 +152,26 @@ class LiteEthIPRX(Module):
                        ).Else(
                                NextState("DROP")
                        )
-               ),
-               fsm.act("PRESENT",
-                       source.stb.eq(sink.stb),
+               )
+               self.comb += [
                        source.sop.eq(sink.sop),
                        source.eop.eq(sink.eop),
-                       sink.ack.eq(source.ack),
                        source.length.eq(sink.total_length - (sink.ihl*4)),
                        source.protocol.eq(sink.protocol),
                        source.ip_address.eq(sink.target_ip),
                        source.data.eq(sink.data),
-                       source.error.eq(sink.error),
+                       source.error.eq(sink.error)
+               ]
+               fsm.act("PRESENT",
+                       source.stb.eq(sink.stb),
+                       sink.ack.eq(source.ack),
                        If(source.stb & source.eop & source.ack,
                                NextState("IDLE")
                        )
                )
                fsm.act("DROP",
                        sink.ack.eq(1),
-                       If(source.stb & source.eop & source.ack,
+                       If(sink.stb & sink.eop & sink.ack,
                                NextState("IDLE")
                        )
                )

diff --git a/liteeth/core/udp.py b/liteeth/core/udp.py
index d2f999537f01650179bbda38affb6a2e73f4e790..7a6c503fbb746b9d368b35bc656c893df27be487 100644 (file)
--- a/liteeth/core/udp.py
+++ b/liteeth/core/udp.py
@@ -87,18 +87,20 @@ class LiteEthUDPRX(Module):
                        ).Else(
                                NextState("DROP")
                        )
-               ),
-               fsm.act("PRESENT",
-                       source.stb.eq(sink.stb),
+               )
+               self.comb += [
                        source.sop.eq(sink.sop),
                        source.eop.eq(sink.eop),
-                       sink.ack.eq(source.ack),
                        source.src_port.eq(sink.src_port),
                        source.dst_port.eq(sink.dst_port),
                        source.ip_address.eq(0),
                        source.length.eq(sink.length - udp_header_len),
                        source.data.eq(sink.data),
-                       source.error.eq(sink.error),
+                       source.error.eq(sink.error)
+               ]
+               fsm.act("PRESENT",
+                       source.stb.eq(sink.stb),
+                       sink.ack.eq(source.ack),
                        If(source.stb & source.eop & source.ack,
                                NextState("IDLE")
                        )