radeonsi: add some missing register definitions

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

diff --git a/src/gallium/drivers/radeonsi/sid.h b/src/gallium/drivers/radeonsi/sid.h
index 3241725ca994059126ac9bffbe0061eb4ccf8949..c4d4afd6f024a2a6c696aa36d30de25390016b66 100644 (file)
--- a/src/gallium/drivers/radeonsi/sid.h
+++ b/src/gallium/drivers/radeonsi/sid.h
@@ -4829,6 +4829,9 @@
 #define   S_00B32C_EXCP_EN(x)                                         (((x) & 0x7F) << 8) /* mask is 0x1FF on CIK */
 #define   G_00B32C_EXCP_EN(x)                                         (((x) >> 8) & 0x7F) /* mask is 0x1FF on CIK */
 #define   C_00B32C_EXCP_EN                                            0xFFFF80FF /* mask is 0x1FF on CIK */
+#define   S_00B32C_LDS_SIZE(x)                                        (((x) & 0x1FF) << 20) /* CIK, for on-chip GS */
+#define   G_00B32C_LDS_SIZE(x)                                        (((x) >> 20) & 0x1FF) /* CIK, for on-chip GS */
+#define   C_00B32C_LDS_SIZE                                           0xE00FFFFF /* CIK, for on-chip GS */
 #define R_00B330_SPI_SHADER_USER_DATA_ES_0                              0x00B330
 /* CIK */
 #define R_00B41C_SPI_SHADER_PGM_RSRC3_HS                                0x00B41C
@@ -6627,15 +6630,35 @@
 #define   C_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS                 0x7FFFFFFF
 #define R_028804_DB_EQAA                                                0x028804
 #define   S_028804_MAX_ANCHOR_SAMPLES(x)               (((x) & 0x7) << 0)
+#define   G_028804_MAX_ANCHOR_SAMPLES(x)               (((x) >> 0) & 0x7)
+#define   C_028804_MAX_ANCHOR_SAMPLES                  (~(((~0) & 0x7) << 0))
 #define   S_028804_PS_ITER_SAMPLES(x)                  (((x) & 0x7) << 4)
+#define   G_028804_PS_ITER_SAMPLES(x)                  (((x) >> 4) & 0x7)
+#define   C_028804_PS_ITER_SAMPLES                     (~(((~0) & 0x7) << 4))
 #define   S_028804_MASK_EXPORT_NUM_SAMPLES(x)          (((x) & 0x7) << 8)
+#define   G_028804_MASK_EXPORT_NUM_SAMPLES(x)          (((x) >> 8) & 0x7)
+#define   C_028804_MASK_EXPORT_NUM_SAMPLES             (~(((~0) & 0x7) << 8))
 #define   S_028804_ALPHA_TO_MASK_NUM_SAMPLES(x)                (((x) & 0x7) << 12)
+#define   G_028804_ALPHA_TO_MASK_NUM_SAMPLES(x)                (((x) >> 12) & 0x7)
+#define   C_028804_ALPHA_TO_MASK_NUM_SAMPLES           (~(((~0) & 0x7) << 12))
 #define   S_028804_HIGH_QUALITY_INTERSECTIONS(x)       (((x) & 0x1) << 16)
+#define   G_028804_HIGH_QUALITY_INTERSECTIONS(x)       (((x) >> 16) & 0x1)
+#define   C_028804_HIGH_QUALITY_INTERSECTIONS          (~(((~0) & 0x1) << 16))
 #define   S_028804_INCOHERENT_EQAA_READS(x)            (((x) & 0x1) << 17)
+#define   G_028804_INCOHERENT_EQAA_READS(x)            (((x) >> 17) & 0x1)
+#define   C_028804_INCOHERENT_EQAA_READS               (~(((~0) & 0x1) << 17))
 #define   S_028804_INTERPOLATE_COMP_Z(x)               (((x) & 0x1) << 18)
+#define   G_028804_INTERPOLATE_COMP_Z(x)               (((x) >> 18) & 0x1)
+#define   C_028804_INTERPOLATE_COMP_Z                  (~(((~0) >> 18) & 0x1))
 #define   S_028804_INTERPOLATE_SRC_Z(x)                        (((x) & 0x1) << 19)
+#define   G_028804_INTERPOLATE_SRC_Z(x)                        (((x) >> 19) & 0x1)
+#define   C_028804_INTERPOLATE_SRC_Z                   (~(((~0) & 0x1) << 19))
 #define   S_028804_STATIC_ANCHOR_ASSOCIATIONS(x)       (((x) & 0x1) << 20)
+#define   G_028804_STATIC_ANCHOR_ASSOCIATIONS(x)       (((x) >> 20) & 0x1)
+#define   C_028804_STATIC_ANCHOR_ASSOCIATIONS          (~(((~0) & 0x1) << 20))
 #define   S_028804_ALPHA_TO_MASK_EQAA_DISABLE(x)       (((x) & 0x1) << 21)
+#define   G_028804_ALPHA_TO_MASK_EQAA_DISABLE(x)       (((x) >> 21) & 0x1)
+#define   C_028804_ALPHA_TO_MASK_EQAA_DISABLE          (~(((~0) & 0x1) << 21))
 #define R_028808_CB_COLOR_CONTROL                                       0x028808
 #define   S_028808_DEGAMMA_ENABLE(x)                                  (((x) & 0x1) << 3)
 #define   G_028808_DEGAMMA_ENABLE(x)                                  (((x) >> 3) & 0x1)