---------- Begin Simulation Statistics ----------
-host_inst_rate 524923 # Simulator instruction rate (inst/s)
-host_mem_usage 203516 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 2843944401 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000032 # Number of seconds simulated
sim_ticks 32088000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1077 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4872000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.074742 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 4611000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 2856000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 2703000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 87.458397 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.021352 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1951 # number of overall hits
-system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 138 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 266984 # Simulator instruction rate (inst/s)
+host_tick_rate 1467506046 # Simulator tick rate (ticks/s)
+host_mem_usage 241568 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+sim_insts 5827 # Number of instructions simulated
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 8 # Number of system calls
+system.cpu.numCycles 64176 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 5827 # Number of instructions executed
+system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
+system.cpu.num_func_calls 194 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
+system.cpu.num_int_insts 5126 # number of integer instructions
+system.cpu.num_fp_insts 2 # number of float instructions
+system.cpu.num_int_register_reads 7300 # number of times the integer registers were read
+system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
+system.cpu.num_mem_refs 2090 # number of memory refs
+system.cpu.num_load_insts 1164 # Number of load instructions
+system.cpu.num_store_insts 926 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 64176 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 13 # number of replacements
+system.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use
+system.cpu.icache.total_refs 5526 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 132.493866 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.064694 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 5526 # number of ReadReq hits
+system.cpu.icache.demand_hits 5526 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 5526 # number of overall hits
+system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
+system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 303 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.051981 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate 0.051981 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.051981 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
-system.cpu.icache.demand_hits 5526 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.051981 # miss rate for demand accesses
-system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
+system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.051981 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 132.493866 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.064694 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate 0.051981 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 5526 # number of overall hits
-system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.051981 # miss rate for overall accesses
-system.cpu.icache.overall_misses 303 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.051981 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 13 # number of replacements
-system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use
-system.cpu.icache.total_refs 5526 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2652000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2040000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 87.458397 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.021352 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 1077 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits
+system.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 1951 # number of overall hits
+system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses
+system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 138 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 4872000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 2856000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.074742 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
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+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 4611000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 2703000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 188.045319 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.005739 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
+system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 2 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 439 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 20176000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 2652000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 22828000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 22828000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 15520000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 22828000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 15520000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2040000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 17560000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 17560000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 188.045319 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.005739 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 22828000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 439 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 17560000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 64176 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 64176 # Number of busy cycles
-system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
-system.cpu.num_fp_insts 2 # number of float instructions
-system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
-system.cpu.num_func_calls 194 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 5827 # Number of instructions executed
-system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
-system.cpu.num_int_insts 5126 # number of integer instructions
-system.cpu.num_int_register_reads 7301 # number of times the integer registers were read
-system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
-system.cpu.num_load_insts 1164 # Number of load instructions
-system.cpu.num_mem_refs 2090 # number of memory refs
-system.cpu.num_store_insts 926 # Number of store instructions
-system.cpu.workload.num_syscalls 8 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff