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diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index a5a271aae20f0bccaef5a9c12c8cd87f52745e68..34c1024bad8b07e69e85050eb8f2950a1bc5fe7f 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -47,9 +47,7 @@ The Mode table for Arithmetic and Logical operations
 | 0-1 |  2  |  3   4  |  description              |
 | --- | --- |---------|-------------------------- |
 | 00  |   0 |  dz  sz | simple mode                      |
-| 00  |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
-| 00  |   1 | SVM 0   | subvector reduce mode, SUBVL>1   |
-| 00  |   1 | /   1   | reserved   |
+| 00  |   1 | 0  RG   | scalar reduce mode (mapreduce) |
 | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
 | 01  | inv | VLi RC1 |  Rc=0: ffirst z/nonz |
 | 10  |   N | dz   sz |  sat mode: N=0/1 u/s |
@@ -63,7 +61,6 @@ Fields:
 * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
 * **RG** inverts the Vector Loop order (VL-1 downto 0) rather
 than the normal 0..VL-1
-* **SVM** sets "subvector" reduce mode
 * **N** sets signed/unsigned saturation.
 * **RC1** as if Rc=1, stores CRs *but not the result*
 * **VLi** VL inclusive: in fail-first mode, the truncation of