soc/integration/soc_core: list rocket as supported CPU

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 7d48f24825e235a935cbc01046341f95b204b590..4e03b5317074bc36dc1248a3b680fb7265811fc7 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -576,7 +576,7 @@ class SoCCore(Module):
 
 def soc_core_args(parser):
     parser.add_argument("--cpu-type", default=None,
-                        help="select CPU: lm32, or1k, picorv32, vexriscv, minerva")
+                        help="select CPU: lm32, or1k, picorv32, vexriscv, minerva, rocket")
     parser.add_argument("--cpu-variant", default=None,
                         help="select CPU variant")
     parser.add_argument("--integrated-rom-size", default=None, type=int,